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SY58610U Datasheet(PDF) 2 Page - Micrel Semiconductor

Part No. SY58610U
Description  3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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SY58610U Datasheet(HTML) 2 Page - Micrel Semiconductor

 
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Micrel, Inc.
SY58610U
November 2006
2
M9999-111406-A
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58610UMG
MLF-16
Industrial
610U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY58610UMGTR
(2)
MLF-16
Industrial
610U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
Truth Table
16-Pin MLF
® (MLF-16)
SEL
Output
0
IN0 Selected
1
IN1 Selected
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” subsection.
2, 3
VREF-AC0,
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN
and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its
respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface Applications”
subsection.
5, 6
15, 16
IN1, /IN1
IN0, /IN0
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of the pairs
internally terminates with 50Ω to the corresponding VT pin. If the input swing falls below a
certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output
by latching the output to its last valid state. See “Input Interface Applications” subsection.
7
SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will
default to logic HIGH state if left open. The input-switching threshold is VCC/2.
8, 13
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC
pins as possible.
9, 12
/Q, Q
LVPECL Differential Output Pair: Differential buffered output copy of the selected input signal.
The output swing is typically 800mV. Unused output pair may be left floating with no impact on
jitter. See “LVPECL Output Termination” subsection.
10, 11
GND,
Exposed Pad
Ground. Exposed pad must be connected to a ground plane that is the same potential as the
ground pins.
14
NC
No connect.


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