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PCF85116-3 Datasheet(PDF) 12 Page - NXP Semiconductors

Part No. PCF85116-3
Description  2048 x 8-bit CMOS EEPROM with I2C-bus interface
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF85116-3 Datasheet(HTML) 12 Page - NXP Semiconductors

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Philips Semiconductors
PCF85116-3
2048
× 8-bit CMOS EEPROM with I2C-bus interface
Product data
Rev. 04 — 25 October 2004
12 of 21
9397 750 14217
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. I2C-bus characteristics
[1]
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
[2]
Cb = total capacitance of one bus line in pF.
Table 8:
I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure 9.
Symbol
Parameter
Conditions
Standard mode
Fast mode
Unit
Min
Max
Min
Max
fSCL
clock frequency
0
100
0
400
kHz
tBUF
time the bus must be free before
new transmission can start
4.7
-
1.3
-
µs
tHD;STA
START condition hold time after
which first clock pulse is generated
4.0
-
0.6
-
µs
tLOW
LOW level clock period
4.7
-
1.3
-
µs
tHIGH
HIGH level clock period
4.0
-
0.6
-
µs
tSU;STA
set-up time for START condition
repeated start
4.7
-
0.6
-
µs
tHD;DAT
data hold time
for CBUS compatible masters
5
-
-
-
µs
for I2C-bus devices
[1]
0-
0
-
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tr
SDA and SCL rise time
-
1000
20 + 0.1Cb[2] 300
µs
tf
SDA and SCL fall time
-
300
20 + 0.1Cb[2] 300
ns
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
µs
P = STOP condition; S = START condition.
Fig 9.
Timing requirements for the I2C-bus.
MBA705
t BUF
HD;STA
t
SCL
SDA
P
S
t LOW
t r
HD;DAT
t
SU;DAT
t
t f
t HIGH
S
HD;STA
t
SU;STA
t
SU;STO
t
P


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