6.42

2

IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is trig gered by a combination of the

rising edge of CLK and

ADSC Low or ADSP Low and CE Low.

ADSC

Address Status

(Cache Controller)

I

LOW

Synchronous Address Status from Cache Controller.

ADSC is an active LOW input that is

used to load the address registers with new addresses.

ADSP

Address Status

(Processor)

I

LOW

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to

load the address registers with new addresses.

ADSP is gated by CE.

ADV

Burst Address

Advance

I

LOW

Synchronous Address Advance.

ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

input is HIGH the burst counter is not incremented; that is, there is no address advance.

BWE

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs

rising edge of CLK then

BWx inputs are passed to the next stage in the circuit. If BWE is

HIGH then the byte write inputs are blocked and only

GW can initiate a write cycle.

Individual Byte

Write Enables

I

LOW

Synchronous byte write enables.

Any active byte write causes all outputs to be disabled.

CE

Chip Enable

I

LOW

Synchronous chip enable.

CE also gates ADSP.

CLK

Clock

I

N/A

This is the clock input. All timing references for the device are made with respect to this

input.

Chip Select 0

I

HIGH

Chip Select 1

I

LOW

Synchronous active LOW chip select.

GW

Global Write

Enable

I

LOW

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK.

GW supersedes individual byte write enables.

Data Input/Output

I/O

N/A

Synchro nous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

LBO

Linear Burst Order

I

LOW

Asynchronous burst order selection input. When

LBO is HIGH, the interleaved burst

sequence is selected. When

LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

OE

Output Enable

I

LOW

Asynchronous output enable. When

OE is LOW the data output drivers are enabled on the

I/O pins if the chip is also selected. When

OE is HIGH the I/O pins are in a high-

impedance state.

Power Supply

N/A

N/A

3.3V core power supply.

Power Supply

N/A

N/A

2.5V I/O Supply.

Ground

N/A

N/A

Ground.

NC

No Connect

N/A

N/A

NC pins are not electrically connected to the device.

ZZ

Sleep Mode

I

HIGH

Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V25761/781 to its lowest p ower consumption level. Data retention is guaranteed in

Sleep Mode.

5297 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.