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LXP730 Datasheet(PDF) 56 Page - Intel Corporation |
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LXP730 Datasheet(HTML) 56 Page - Intel Corporation |
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56 / 70 page  LXP730 — Multi-Rate DSL Framer 56 Datasheet 5.6 Slip Buffer Lower Threshold Register Address: 18 Abbreviation: SLP_THDL Read/Write Table 47. FIFO/Miscellaneous Control Register Bit Name Default Description <7:6> SAPCLKDIV 00b Async serial port clock select, 0 = MCLK/2, 1 = MCLK/4, 2 = MCLK/ 8, 3 = MCLK/16. 5 TX8KSSEL 0 Transmit 8 KHz reference sync select control. 0 = TX reference sync selected from PCM interface, 1 = TX reference sync selected from codec interface. 4 REMOTE_LB 0 Remote Loopback select. Controls the scrambling polynomial for remote loopback. 0 = normal operation, 1 = remote loopback. 3PDOE_SEL0 PCM data output enable select. Default value of 0 causes pin to be FRMSYNC12 for codec operation. Set to 1 to create the output enable signal PDOE for PCM usage. PDOE goes high for programmed PCM time slots in the Nx registers. 2DXFIFORXT 0 DX FIFO reset control. The DX elastic store FIFO is reset on a 0 to a 1 transition. The 0 or 1 state must be active for a minimum of 3 BITCLK periods. 1 MXFIFORXT 0 MX FIFO reset control. The MX elastic store FIFO is reset on a 0 to a 1 transition. The 0 or 1 state must be active for a minimum of 3 BITCLK periods. 0 FIX2BSTUF 0 Fixed 2-bit stuffing mode enable; 0 = disable, 1 = enable. Table 48. Slip Buffer Lower Threshold Bit Name Default Description <7> SLP_L_EN 0 0 = Use default, 1 = Enable and use Bits <6:0> for the Lower Threshold. Must be set when Stopped (Run/Stop = 0). <6:0> SLP_LWR 0 MPC Mode: Lower Threshold of PCM Receive Slip Buffer (Default 31-N). HWC Mode: Not Used. |
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