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LH77790B Datasheet(PDF) 7 Page - Sharp Corporation |
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LH77790B Datasheet(HTML) 7 Page - Sharp Corporation |
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7 / 32 page  LH77790B Thermal & Electrical Specification 5 Pin Description Table 1. Pin Descriptions PINS NAME DIRECTION DESCRIPTION EXTERNAL BUS INTERFACE 36 - 31, 28 - 21, 18 - 11, 8 - 5 A[25:0] O External Address bus. The 790B will provide a 26-bit address to exter- nal memories and peripherals. 60 - 55, 52 - 47, 42 - 41, 38 - 37 D[15:0] I/O External 16-Bit data bus. 72 OE O Output Enable for external memory and peripherals. OE allows external memory and peripherals to drive the data bus and is asserted LOW dur- ing a read access and HIGH during a write access. 71 WE O Write Enable for external memory and peripherals. During a write access, this pin is driven LOW. During a read access, this pin is driven HIGH. 70 - 65 CE[5:0]/ CAS[5:0] O These pins provide the Chip Enable/Column Address Select signals al- lowing direct connection to standard external memory/peripheral devic- es. The pins act as CAS when interfacing to DRAMs and as CE otherwise. They are fully programmable by the system designer and can support byte enables. 62 - 61 RAS[1:0] O Row Address Select pins for DRAM Bank 0 and Bank 1. 74 WAIT I External Memory Wait. Allows the use of slow memories. The 790B generates external WAIT cycles (EWC) in response to activating WAIT. WAIT is sampled on the HIGH to LOW transition on XCLK. To add one EWC, WAIT must be active prior to sampling in the last cycle (beginning of the last cycle) of a memory transfer. If WAIT continues to be active (when sampled) in subsequent cycles, more EWC will be added. Once WAIT is deactivated, the 790B will complete the memory transfer. 73 BW O Byte Wide Access. BW is LOW when the ARM7DI executes a store/ load byte instruction. BW is HIGH when the ARM7DI Core executes a store/load word instruction or an instruction fetch. BW does not depend on the bus size of the external memory/peripheral device. BW is valid during an external memory access. It can be used by an external ad- dress decoder to generate extra chip/byte enables. BW is a don't care during DRAM refresh. 169 BB I Byte Boot selects between x8 or x16 for the boot memory. The 790B samples and captures the state of BB on the rising edge of RESETI allowing BB to change state after Reset. If BB is LOW the 790B will boot from a x8 memory. If BB is HIGH, the 790B will boot from a x16 mem- ory. This pin is normally tied LOW for x8 boot memory or HIGH for x16 boot memory. COUNTERS/TIMERS INTERFACE 123, 121, 117 CTGATE[2:0] I Counter/Timer control gate input signals. 124, 122, 118 CTOUT[2:0] O Counter/Timer output signals. INTERRUPT INTERFACE 107 - 102 INT[5:0] I External interrupt input signals. |
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