IR3621&(PbF)

5

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PIN DESCRIPTIONS

1

2

3

4

5,23

6,22

7,21

8

20

9,19

10,18

11,17

12,16

13,15

14

24

25

26

27

28

Power Good pin. Low when any of the outputs fall 10% below the set voltages.

Supply voltage for the internal blocks of the IC. The Vcc slew rate should be

<0.1V/us.

Output of the internal LDO. Connect a 1.0uF capacitor from this pin to ground.

Connecting a resistor from this pin to ground sets the oscillator frequency.

Sense pins for OVP and PGood. For current share tie these pins together.

Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is con-

nected to a resistor divider to set the output voltage and Fb2 is connected to

programming resistor to achieve current sharing. In independent 2-channel mode,

these pins work as feedback inputs for each channel.

Compensation pins for the error amplifiers.

These pins provide user programmable soft-start function for each outputs.

Connect external capacitors from these pins to ground to set the start up time

for each output. These outputs can be shutdown independently by pulling the

respective pins below 0.3V. During shutdown both MOSFETs will be turned off.

For current share mode SS2 must be floating.

A resistor from these pins to switching point will set current limit threshold.

Supply voltage for the high side output drivers. These are connected to voltages

that must be typically 6V higher than their bus voltages. A 0.1

µF high fre-

quency capacitor must be connected from these pins to PGND to provide peak

drive current capability.

Output drivers for the high side power MOSFETs. Note3

These pins serve as the separate grounds for MOSFET drivers and should be

connected to the system’s ground plane.

Output drivers for the synchronous power MOSFETs.

Supply voltage for the low side output drivers.

The internal oscillator can be synchronized to an external clock via this pin.

When pulled High, it puts the device current limit into a hiccup mode. When

pulled Low, the output latches off, after an overcurrent event.

Non-inverting input to the second error amplifier. In the current sharing mode, it

is connected to the programming resistor to achieve current sharing. In inde-

the resistor divider to set the output voltage.

Reference Voltage. The drive capability of this pin is about 2

µA.

Analog ground for internal reference and control circuitry.

TSSOP

MLPQ

PIN SYMBOL

PIN DESCRIPTION

29

30

31

1

2,22

3,21

4,20

5

19

6,18

7,17

8,16

10,14

11,13

12

23

24

26

27

28

9,15,25.32

PGood

Vcc

Rt

Fb2,Fb1

Comp2, Comp1

SS2 / SD

SS1 / SD

OCSet2,OCSet1

VcH2, VcH1

HDrv2, HDrv1

PGnd2, PGnd1

LDrv2, LDrv1

Sync

Hiccup

Gnd

N/C

Note3: The negative voltage at these pins may cause instability for the gate drive circuits. To prevent this, a low

forward voltage drop diode (Schottky) is required between these pins and power ground.

No Connect