2

EPSON ELECTRONICS AMERICA, INC.

i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238

ASIC

S1L50000

DATA SHEET

The S1L50000 Series comprises 11 types of masters, from which the customer is able to select

the master most suitable.

Cell Utilization Ratio (U)

*1

Master

Total

BC

(Raw Gates)

Number

of

Pads

Number

of

Columns (X)

Number

of

Rows (Y)

2-layer

metal

3-layer

metal

4-layer

metal

S1L50282/283/284

28710

88

319

90

50%

88%

95%

S1L50752/753/754

75774

144

519

146

47%

85%

95%

S1L50992/993/994

99198

168

594

167

47%

85%

95%

S1L51252/253/254

125772

188

669

188

45%

80%

95%

S1L51772/773/774

177062

224

794

223

45%

75%

95%

S1L52502/503/504

250160

264

944

265

45%

75%

95%

S1L53352/353/354

335858

308

1094

307

43%

75%

95%

S1L54422/423/424

442112

352

1256

352

40%

70%

90%

S1L55062/063/064

506688

376

1344

377

40%

70%

90%

S1L56682/683/684

668552

432

1544

433

40%

70%

90%

S1L58152/153/154

815468

480

1706

478

40%

70%

90%

NOTE:

the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only

as an estimate