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ADS5546IRGZR Datasheet(PDF) 37 Page - Texas Instruments |
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ADS5546IRGZR Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 50 page  www.ti.com Programmable Gain Power Down ADS5546 SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006 APPLICATION INFORMATION (continued) Table 9. Clock Buffer Gain Programming REGISTER ADDRESS REGISTER DATA DESCRIPTION A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 <CLK GAIN> – Clock buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 Gain 4 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 Gain 3 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 Gain 2 0 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 Gain 1 Default gain 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 Gain 0 Minimum gain ADS5546 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range varies from 2 VPP down to 1 VPP, with 0 dB being the default gain. At high IF, this is especially useful as the SFDR improvement is significant with marginal degradation in SNR. The gain can be programmed using the serial interface (bits D3-D0 in register 0x68). Table 10. Programmable Gain REGISTER ADDRESS REGISTER DATA DESCRIPTION A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 <GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 VPP compared to 2 VPP at 0 dB gain. 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 dB Default after reset 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 dB 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 2 dB 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 1 3 dB 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 4 dB 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 5 dB 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 6 dB ADS5546 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped. Global STANDBY This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powered down and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state. The wake-up time from the global power down to data becoming valid normal mode is maximum 100 µs. Output Buffer Disable The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total power by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time from this mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOS mode. Input Clock Stop The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum 100 µs. 37 Submit Documentation Feedback |
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