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DATA SHEET

EPSON ELECTRONICS AMERICA, INC.

i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238

ASIC

S1L50000

S1L50000 SERIES HIGH DENSITY GATE ARRAY

EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS

gate array utilizing a 0.35

µm “sea-of-gates” architecture. The S1L50000H products feature 5V

tolerant I/O buffers.

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Ultra-high-speed, high density and low power consumption

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Low voltage operation: 3.3V and 2.0V

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Number of raw gates: 28,710 ~ 815,468 gates

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Process

0.35

µm 2/3/4 layer metalization CMOS process

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Integration

A maximum of 815,468 gates (2 input NAND gate equivalent)

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Operating Speed

Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)

(2-input pair NAND, F/O = 2, Typical wire load)

Input buffer:

380 ps (5.0V Typ) Built-in level shifter is used.

400 ps (3.3V Typ), 1.30 ns (2.0V Typ)

(F/O = 2, Typical wire load)

Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.

2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)

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I/F Levels

Input/Output TTL/CMOS/LVTTL compatible

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Input Modes

TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI

Built-in pull-up and pull-down resistors can be usable.

(2 types for each resistor value)

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Output Modes

Normal, 3-state, bi-directional, PCI

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Output Drive

(Built-in level shifter is used at 5.0V)

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RAM

Asynchronous 1-port, asynchronous 2-port

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Dual Power

Operation supported by using level-shifter circuit

Internal logic: Operation supported by low voltage

I/O Buffer:

Built-in interfaces of both high and low voltages possible

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± 0.2V