9

DATA SHEET

EPSON ELECTRONICS AMERICA, INC.

i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238

ASIC

S1L50000

Delivery Spec.

Approval

GATE ARRAY DEVELOPMENT FLOW

CUSTOMER

EEA

Product Plan

Functional Spec.

Circuit Design

Test Pattern Design

Logical Check

(Simulation)

Verification

ET(TS) Approve

the Prototype

Approve Delivery

Spec.

Delivery Spec.

ES(TS) Proto.

Approval

Customer Spec.

(Sign Off)

Simulation List

MP

Delivery Spec.

Publication

MP Setup

ES (Engr. Sample)

Fabrication

TS (Test Sample)

Fabrication

Make Masks

Post Simulation

Place & Route

Timing Check

(Simulation)

* Jobs are done by customer and EEA engineer. Steps in shadowed boxes are based on customer’s requirement.

NOTE:

When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc.,

the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design).

Verification

Verification

Verification

G/A Development

Request

Simulation

File

•Schematic

•Pin assignment

•Timing wave form

•Marking diagram

•P/O

Schematic Pin

G/A Development

Request

•Test pattern (timing chart)

•Timing wave form

•Marking diagram

•P/O

Assignment

Logical Check

(Simulation)

Check

Check

OK

NG

OK

NG

OK

NG

NG

EWS

OK

NG

OK

NG

OK

Delay Analyzing

Delay Analyzing

*

*

1

2

Refer to Note