PS2500 2.2 GHz Fractional-N Frequency Synthesizer
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Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
• Main Dividend MSB Register (at which point the new divide ratio takes effect).
In applications where the main synthesizer is in 10-bit mode, the Main Dividend MSB Register holds the 10
bits of the dividend. The order in which the registers controlling the main synthesizer’s divide ratio are to
be loaded is:
• Main Divider Register
• Main Dividend MSB Register (at which point the new divide ratio takes effect).
For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The order
in which the registers controlling the auxiliary synthesizer’s divide ratio is to be loaded is:
• Auxiliary Divider Register
• Auxiliary Dividend Register (at which point the new divide ratio takes effect).
Note: When in integer mode, the new divide ratios take effect as soon as the Main or Auxiliary Divider
Register is loaded.
Direct Digital Modulation
The PS2500’s high fractionality and small step size permit the user to tune to practically any frequency in
the VCO’s operating range. This frequency tuning permits direct digital modulation by programming the
different desired frequencies at precise instants. Typically, the channel frequency is selected through the
main divider and dividend register and the instantaneous frequency offset from the carrier is entered
through the modulation data register.
Write access to the modulation data register can be performed three ways:
Normal register write
A normal 16-bit serial interface write to the modulation data register at address Hex9 where /CS is 16
Clock cycles wide and modulation data is presented on the Data pin. The content of the modulation data
register is passed to the modulation unit at the next falling edge of the divided main VCO frequency
(Fpd_main).
Short /CS through Data pin (no address bits required)
A shortened serial interface write where /CS is from 2 to 12 Clock cycles wide and modulation data (2 to
12 bits) is presented on the Data pin. The Data is the default pin for entering modulation data directly in
modulation data register with shortened /CS strobes. This method of data entry eliminates the register
address overhead on the serial interface. All serial interface bits are re-synchronized internally at the
reference oscillator frequency. The content of the modulation data register is passed to the modulation unit
at the next falling edge of the divided main VCO frequency (Fpd_main).
Short /CS through Mod_in pin (no address bits required)
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