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74LVT16646 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LVT16646 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 9 page 
www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Truth Table (Note 1) H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level = LOW-to-HIGH Transition. Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins. Pin Names Description A0–A15 Data Register A Inputs/3-STATE Outputs B0–B15 Data Register B Inputs/3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OE1, OE2 Output Enable Inputs DIRn Direction Control Inputs Inputs Data I/O Output Operation Mode OE1 DIR1 CPAB1 CPBA1 SAB1 SBA1 A0–7 B0–7 H X H or L H or L X X Isolation HX X X X Input Input Clock An Data into A Register HX X X X Clock Bn Data Into B Register LH X X L X An to Bn—Real Time (Transparent Mode) LH X L X Input Output Clock An Data to A Register L H H or L X H X A Register to Bn (Stored Mode) LH X H X Clock An Data into A Register and Output to Bn L L XXX L Bn to An—Real Time (Transparent Mode) LL X X L Output Input Clock Bn Data into B Register L L X H or L X H B Register to An (Stored Mode) LL X X H Clock Bn into B Register and Output to An |
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