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74LVT16646 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. 74LVT16646
Description  Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74LVT16646 Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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© 2001 Fairchild Semiconductor Corporation
DS012023
www.fairchildsemi.com
January 2000
Revised October 2001
74LVT16646 • 74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVT16646 and LVTH16646 contains sixteen non-
inverting bidirectional registered bus transceivers providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Each byte has sepa-
rate control inputs which can be shorted together for full
16-bit operation. The DIR inputs determine the direction of
data flow through the device. The CPAB and CPBA inputs
load data into the registers on the LOW-to-HIGH transition
(see Functional Description).
The LVTH16646 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT16646 and
LVTH16646 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16646)
s Also available without bushold feature (74LVT16646)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides
glitch-free bus loading
s Outputs source/sink
−32 mA/+64 mA
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human-body model
> 2000V
Machine model
> 200V
Charged-device model
> 1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number
Package Number
Package Description
74LVT16646MEA
(Preliminary)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16646MTD
(Preliminary)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16646MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide


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