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HDSP2110S Datasheet(PDF) 2 Page - Infineon Technologies AG

Part # HDSP2110S
Description  8-Character 5x7 Dot Matrix Parallel Input Alphanumeric Intelligent Display
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

HDSP2110S Datasheet(HTML) 2 Page - Infineon Technologies AG

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 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
HDSP2110S/1S/2S/3S/4S/5S
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
2
March 24, 2000-13
Maximum Ratings (TA=25°C)
DC Supply Voltage, VCC to GND
(max. voltage with no LEDs on) ...................–0.3 to +7.0 VDC
Input Voltage Levels,
All Inputs ....................................................... –0.3 to VCC +0.3
Operating Temperature ....................................... –40
°C to 85°C
Storage Temperature ......................................... –40
°C to 100°C
Relative Humidity (non-condensing) ....................................85%
Operating Voltage, VCC to GND
(Max. voltage with 20 dots/digits on).............................. 5.5 V
Maximum Solder Temperature
(0.063" below seating plane, t<5.0 s)............................ 260
°C
ESD Protection at 1.5 k
Ω,
100 pF .....................................................VZ=4.0 kV (each pin)
Figure 1. Enlarged Character Font
Figure 2. Write Cycle Timing Diagram
Input pulse levels –0.6 V to 2.4 V
ESD Warning:
Standard precautions for CMOS
handling should be observed.
0.112
(2.85)
0.030 (0.76) Typ.
0.01 (0.254)
0.026 (0.65) Typ.
0.189
(4.81)
R1
R2
R3
R4
R5
R6
R7
C1 C2 C3 C4 C5
Dimensions in inches (mm)
Tacc
Twd
Tdh
Tw
Tces
Tcer
Tceh
Tacs
Tach
Tacs
A0-A3
FL
Tce
CE
WR
D0-D7
Input pulse levels —0.6 V to 2.4 v
Switching Specifications
(over operating temperature range and VCC=4.5 V)
Symbol
Description
Min.
Units
Tacc
Display Access Time—Write
210
ns
Tacc
Display Access Time—Read
230
ns
Tacs
Address Setup Time to CE
10
ns
Tce
Chip Enable Active Time—Write
140
ns
Tce
Chip Enable Active Time—Read
160
ns
Tach
Address Hold Time to CE
20
ns
Tcer
Chip Enable Recovery Time
60
ns
Tces
Chip Enable Active Prior to
Rising Edge—Write
140
ns
Tces
Chip Enable Active Prior to
Rising Edge—Read
160
ns
Tceh
Chip Enable Hold to Rising Edge
of Read/Write Signal
0ns
Tw
Write Active Time
100
ns
Twd
Data Valid Prior to
Rising Edge of Write Signal
50
ns
Tdh
Data Write Time
20
ns
Tr
Chip Enable Active Prior to Valid
Data
160
ns
Trd
Read Active Prior to Valid Data
95
µs
Tdf
Read Data Float Delay
10
ns
Trc
Reset Active Time
300
ns


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