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KM641003B-12 Datasheet(PDF) 2 Page - Samsung semiconductor |
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KM641003B-12 Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 8 page KM641003B CMOS SRAM PRELIMINARY Rev 2.0 - 2 - February 1998 PRELIMINARY Preliminary 256K x 4 Bit (with OE)High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time 8,10,12ns(Max.) • Low Power Dissipation Standby (TTL) : 50 mA(Max.) (CMOS) : 10 mA(Max.) Operating KM641003B - 8 : 150 mA(Max.) KM641003B - 10 : 145 mA(Max.) KM641003B - 12 : 140 mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration KM641003BJ : 32-SOJ-400 The KM641003B is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The KM641003B uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM641003B is packaged in a 400 mil 32-pin plastic SOJ. PIN FUNCTION Pin Name Pin Function A0 - A17 Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O4 Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection PIN CONFIGURATION (Top View) Clk Gen. I/O1 ~ I/O4 CS WE OE FUNCTIONAL BLOCK DIAGRAM Data Cont. Column Select CLK Gen. Pre-Charge Circuit Memory Array 256 Rows 1024x4 Columns I/O Circuit & SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A17 A16 A15 A14 A13 OE I/O4 Vss Vcc I/O3 A12 A11 A10 A9 A8 N.C. N.C. A0 A1 A2 A3 CS I/O1 Vcc Vss I/O2 WE A4 A5 A6 A7 N.C. A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A16A17 |
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