KM641001A

CMOS SRAM

PRELIMINARY

Rev 5.0

- 6 -

February 1998

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

device to device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100%

tested.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and

write cycle.

Address

CS

Valid Data

WE

Data in

Data out

High-Z(8)

High-Z

OE

Address

CS

Valid Data

WE

Data in

Data out

(10)

(9)

High-Z(8)

High-Z