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K6R1004C1B Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6R1004C1B Datasheet(HTML) 5 Page - Samsung semiconductor |
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5 / 8 page 
K6R1004C1B-C CMOS SRAM PRELIMINARY Rev 2.0 - 5 - February 1998 PRELIMINARY Preliminary WRITE CYCLE Parameter Symbol K6R1004C1B-8 K6R1004C1B-10 K6R1004C1B-12 Unit Min Max Min Max Min Max Write Cycle Time tWC 8 - 10 - 12 - ns Chip Select to End of Write tCW 6 - 7 - 8 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 6 - 7 - 8 - ns Write Pulse Width(OE High) tWP 6 - 7 - 8 - ns Write Pulse Width(OE Low) tWP1 8 - 10 - 12 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 4 0 5 0 6 ns Data to Write Time Overlap tDW 4 - 5 - 6 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - ns Address Data Out Previous Valid Data Valid Data TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tAA tRC tOH TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) CS Address OE Data out tAA tOLZ tLZ(4,5) tOH tRC tOE tCO tPU tPD tHZ(3,4,5) 50% 50% VCC Current ICC ISB Valid Data tOHZ |
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