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K6R1004C1B Datasheet(PDF) 4 Page - Samsung semiconductor |
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K6R1004C1B Datasheet(HTML) 4 Page - Samsung semiconductor |
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4 / 8 page  K6R1004C1B-C CMOS SRAM PRELIMINARY Rev 2.0 - 4 - February 1998 PRELIMINARY Preliminary TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below AC CHARACTERISTICS(TA=0 to 70 °C, VCC=5.0V±10%, unless otherwise noted.) READ CYCLE Parameter Symbol K6R1004C1B-8 K6R1004C1B-10 K6R1004C1B-12 Unit Min Max Min Max Min Max Read Cycle Time tRC 8 - 10 - 12 - ns Address Access Time tAA - 8 - 10 - 12 ns Chip Select to Output tCO - 8 - 10 - 12 ns Output Enable to Valid Output tOE - 4 - 5 - 6 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 4 0 5 0 6 ns Output Disable to High-Z Output tOHZ 0 4 0 5 0 6 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns Chip Selection to Power DownTime tPD - 8 - 10 - 12 ns Output Loads(B) DOUT 5pF* 480 Ω 255 Ω for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V * Including Scope and Jig Capacitance Output Loads(A) DOUT RL = 50 Ω ZO = 50 Ω VL = 1.5V 30pF* * Capacitive Load consists of all components of the test environment. |
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