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NE56632-43D Datasheet(PDF) 11 Page - NXP Semiconductors |
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NE56632-43D Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 16 page Philips Semiconductors Product data NE56632-XX Active-LOW system reset with adjustable delay time 2002 Mar 25 11 APPLICATION INFORMATION A typical application circuit for the NE56632-XX is shown in Figure 24. Note that a pull-up resistor, RPU is necessary since the output is an open collector. The value of RPU is calculated by the following expression. RPU ≥ (VCC – VRESET) / IOL where: VCC = VS(min) – 0.05 V (for a 3 V reset this is 2.905 V) VRESET = 0.4 V (this is VOL(max)) IOL = 5 mA; minimum output current at Tamb = 25 °C Substituting these values into the expression and calculating, finds RPU should be greater than or equal to 510 Ω. To ensure that the Active-LOW level is sufficient, a value of 4.7 k Ω is chosen in the test and application examples. 12 3 4 5 NE56632-XX RPU TO RESET TERMINAL OF CPU SL01605 CD TO VCC Figure 24. Typical application. Figure 25 (NE56632-20 CD versus tPLH) and Figure 26 (NE56632-44 CD versus tPLH) show how tPHL, the “H” transmission delay or reset release delay time varies as a function of the external delay capacitance, CD. From Figure 26, typical range of the delay capacitance is 1 pF to 10 nF which yields typical delays from 200 µs to 200 ms. The following formula can be used to find the approximate delay time based on external delay capacitance, CD and the delay time coefficient, d shown in Table 2. tPLH (ms) ≈ CD (µF) × d For example, a NE56632-44 using an external capacitor, CD = 1 nF = 1000 pF yields: tPLH (ms) ≈ (1 × 10–3) (1.85 × 104) ≈ 18.5 ms Compare this to the value of tPLH ≈ 17 ms for CD = 1000 pF that is extracted from Figure 26. SL01611 CD (pF) 1.0E+01 1.0E+02 1.0E+03 1.0E+00 1.0E+00 1.0E+04 1.0E–01 1.0E–02 1.0E–03 1.0E–04 1.0E–05 Figure 25. NE56632-20 CD versus tPLH characteristics. SL01612 CD (pF) 1.0E+01 1.0E+02 1.0E+03 1.0E+00 1.0E+00 1.0E+04 1.0E–01 1.0E–02 1.0E–03 1.0E–04 1.0E–05 Figure 26. NE56632-44 CD versus tPLH characteristics. Table 2. Delay time coefficient Device d NE56632–46 1.95 × 104 NE56632–45 1.90 × 104 NE56632–44 1.85 × 104 NE56632–43 1.80 × 104 NE56632–42 1.75 × 104 NE56632–31 1.20 × 104 NE56632–30 1.15 × 104 NE56632–29 1.10 × 104 NE56632–28 1.05 × 104 NE56632–27 1.00 × 104 NE56632–20 0.65 × 104 NE56632–19 0.60 × 104 |
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