K4C89323AF-TCFB datasheet(3/58 Pages) SAMSUNG

Part #	K4C89323AF-TCFB

Description	2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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K4C89363AF

REV. 0.0 Nov. 2002

- 3 -

2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

DESCRIPTION

K4C89363AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89363AF is organized as

2,097,152-words x 4 banks x36 bits. K4C89363AF feature a fully synchronous operation referenced to clock edge whereby all opera-

tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89363AD can

operate fast core cycle compared with regular DDR SDRAM.

K4C89363AF is suitable for Server, Network and other applications where large memory density and low power consumption are

required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.

FEATURES

Parameter

K4C89363AF

F6

FB

F5

t

CK Clock Cycle Time (min)

CL = 4

4.0 ns

4.5 ns

5.0 ns

CL = 5

3.33 ns

3.75 ns

4.5 ns

CL = 6

3.0ns

3.33 ns

4.0 ns

t RC Random Read/Write Cycle Time (min)

20.0 ns

22.5 ns

25 ns

t RAC Random Access Time (min)

20.0 ns

22.5 ns

25 ns

I DD1S Operating Current (single bank) (max)

TBD

I DD2S Power Down Current (max)

TBD

I DD3S Self-Refresh Current (max)

TBD

•

Fully Synchronous Operation

-

Double Data Rate (DDR)

- Data input/output are synchronized with both edges of DS / QS.

-

Differential Clock (CLK and CLK ) inputs

- CS , FN and all address input signals are sampled on the positive edge of CLK.

-

Output data (DQs and QS) is aligned to the crossings of CLK and CLK .

•

Fast clock cycle time of 3.0 ns minimum

-

Clock : 333 MHz maximum

-

Data :

666 Mbps/pin maximum

•

Quad Independent Banks operation

•

Fast cycle and Short Latency

•

Selectable Data Strobe(Uni/Bi-directional data strobe)

•

Distributed Auto-Refresh cycle in 3.9us

•

Self-Refresh

•

Power Down Mode

•

Variable Write Length Control

•

Write Latency = CAS Latency-1

•

Programable CAS Latency and Burst Length

- CAS Laatency = 4, 5, 6

- Burst Length = 2,4

•

Organization : 2,097,152 words x 4 banks x 36 bits

•

Power Supply Voltage V

DD : 2.5V ± 0.125V

•

V DDQ : 1.8V ± 0.1V

•

1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver)

•

Package : 144Ball BGA, 1mm x 0.8mm Ball pitch

•

JTAG(for x36)

•

Notice :

Network-DRAM is trademark of Samsung Electronics., Co LTD

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