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SN74SSTV16859 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. SN74SSTV16859
Description  13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

SN74SSTV16859 Datasheet(HTML) 5 Page - Texas Instruments

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SN74SSTV16859
13BIT TO 26BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V†
UNIT
MIN
MAX
UNIT
fclock
Clock frequency
200
MHz
tw
Pulse duration, CLK, CLK high or low
2.5
ns
tact
Differential inputs active time (see Note 6)
22
ns
tinact
Differential inputs inactive time (see Note 7)
22
ns
tsu
Setup time, fast slew rate (see Notes 8 and 10)
Data before CLK
↑, CLK↓
0.75
ns
tsu
Setup time, slow slew rate (see Notes 9 and 10)
Data before CLK
↑, CLK↓
0.9
ns
th
Hold time, fast slew rate (see Notes 8 and 10)
Data after CLK
↑, CLK↓
0.75
ns
th
Hold time, slow slew rate (see Notes 9 and 10)
Data after CLK
↑, CLK↓
0.9
ns
† For this test condition, VDDQ always is equal to VCC.
NOTES:
6. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken
low.
8. For data signal input slew rate
≥ 1 V/ns
9. For data signal input slew rate
≥ 0.5 V/ns and < 1 V/ns
10. CLK, CLK signals input slew rates are
≥ 1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V†
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
UNIT
fmax
200
MHz
tpd
CLK and CLK
Q
1.1
2.8
ns
tPHL
RESET
Q
5
ns
† For this test condition, VDDQ always is equal to VCC.


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