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LMX2486 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. LMX2486
Description  1.0 GHz - 4.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum TM Frequency Synthesizers with 3.0 GHz Integer PLL
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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LMX2486 Datasheet(HTML) 5 Page - National Semiconductor (TI)

 
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Electrical Characteristics (V
CC = 3.0V; -40˚C
≤ T
A
≤ +85˚C unless otherwise specified) (Continued)
Symbol
Parameter
Conditions
Value
Units
Min
Typ
Max
PHASE NOISE
L
F1HzRF
RF Synthesizer
Normalized Phase Noise
Contribution(Note 6)
RF_CPG = 0
-202
dBc/Hz
RF_CPG = 1
-204
RF_CPG = 3
-206
RF_CPG = 7
-210
RF_CPG = 15
-210
L
F1HzIF
IF Synthesizer
Normalized Phase Noise
Contribution
-209
dBc/Hz
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
V
IH
High-Level Input Voltage
1.6
V
CC
V
V
IL
Low-Level Input Voltage
0.4
V
I
IH
High-Level Input Current V
IH =VCC
-1.0
1.0
µA
I
IL
Low-Level Input Current
V
IL = 0 V
-1.0
1.0
µA
V
OH
High-Level Output
Voltage
I
OH = -500 µA
V
CC-0.4
V
V
OL
Low-Level Output
Voltage
I
OL = 500 µA
0.4
V
MICROWIRE INTERFACE TIMING
t
CS
Data to Clock Set Up
Time
See MICROWIRE Input Timing
25
ns
t
CH
Data to Clock Hold Time See MICROWIRE Input Timing
8
ns
t
CWH
Clock Pulse Width High
See MICROWIRE Input Timing
25
ns
t
CWL
Clock Pulse Width Low
See MICROWIRE Input Timing
25
ns
t
ES
Clock to Load Enable
Set Up Time
See MICROWIRE Input Timing
25
ns
t
EW
Load Enable Pulse
Width
See MICROWIRE Input Timing
25
ns
Note 3: For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Note 4: Refer to table in Section 2.4.2 RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
Note 5: In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset
frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the
impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, VCO Frequency = 3 GHz,
Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
Note 6: Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, ina1Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for
RF_CPG = 7, Fraction = 1/2000, VCO Frequency = 3 GHz, Comparison Frequency = 20 MHz, FM = 0, and DITH = 0.
MICROWIRE INPUT TIMING DIAGRAM
20156975
www.national.com
5


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