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TheseSCLKsareoptional.

CONFIGURE

READResult

READResult

Nth

Nth from#1

Nthfrom#1

Nthfrom#1

Nthfrom#1

Nthfrom#1

N − 1thfrom#2

Nthfrom#3

N − 1thfrom#2

Nthfrom#1

1110............

1101b

1101b

1

16

1

16

1

16

Cascaded ManualTrigger/ReadWhileSampling

(UseinternalCCLK,EOC,and

polarityprogrammedasactivelow)

heldlowduringtheNtimes16bitstransfercycle.

INT

CS

CONVST #1,

CONVST

CONVST

#2,

#3

EOC#1

(activelow)

INT #1

(active low)

CS/FS#3

SCLK#1,

SCLK#2,

SCLK#3

SDO#1,

CDI#2

SDO#2,

CDI#3

SDO#3

SDI#1,

SDI#2,

SDI#3

CS/FS#1

CS/FS#2

SCLK#2,

t

t

t

=

20nsmin

d(EOS-CSF)

t

20nsmin

t

t

=

20nsmin

d(CSR-EOS)

t

20nsmin

t

ADS8329

ADS8330

SLAS516 – DECEMBER 2006

Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The

different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).

The first 16-bit word after the falling chip select is always the data from the chip that received the chip select

signal.

Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and

so on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example,

the same data from the converter is going to be shown repeatedly.

Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the

same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired

result.

Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS

Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters

#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data

downstream.

33

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