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Status Output EOC/INT

Power-Down Modes

0.1

1

10

100

20

10020

20020

30020

40020

Settling Time − ns

ADS8329

ADS8330

SLAS516 – DECEMBER 2006

When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following

manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is

programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has

ended. The EOC output goes low for 3 conversion clocks (CCLK) after the previous rising edge of EOC, if auto

trigger is programmed.

This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is

equal to the conversion time. This status pin can be used as INT. (CFR_D[7:6] = 1, 0) which is set LOW at the

end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either

function (EOC or INT), is programmable through CFR_D7.

The ADS8329/30 has a comprehensive built-in power-down feature. There are three power-down modes: Deep

power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are

enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup

command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works

slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance

(EOC) puts the device into auto nap powerdown. The beginning of sampling resumes operation of the converter.

The contents of the configuration register is not affected by any of the power-down modes. Any ongoing

conversion when nap or deep powerdown is activated is aborted.

Figure 55. Typical Analog Supply Current Drop vs Time After Powerdown

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