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ADS8329 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. ADS8329
Description  LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS8329 Datasheet(HTML) 5 Page - Texas Instruments

 
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SPECIFICATIONS
ADS8329
ADS8330
SLAS516 – DECEMBER 2006
T
A = –40°C to 85°C, +VBD = +VA × 1.5 to +1.65 V, Vref = 2.5 V, fSAMPLE = 1 MHz for 3 V ≤ +VA ≤ 3.6 V, fSAMPLE = 900 kHz for
3 V < +VA
≤ 2.7 V using external clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage (1)
+IN – (–IN) or (+INx – COM)
0
+Vref
V
+IN, +IN0, +IN1
AGND – 0.2
+VA + 0.2
Absolute input voltage
V
–IN or COM
AGND – 0.2
AGND + 0.2
Input capacitance
40
45
pF
No ongoing conversion,
Input leakage current
-1
1
nA
DC Input
At dc
108
Input channel isolation, ADS8330 only
dB
VI = ±1.25 Vpp at 50 kHz
101
SYSTEM PERFORMANCE
Resolution
16
Bits
No missing codes
16
Bits
ADS8329IB,
–1.75
±1
1.75
ADS8330IB
INL
Integral linearity
LSB(2)
ADS8329I, ADS8330I
–2.5
±1.5
2.5
ADS8329IB,
– 1
±0.5
1
Differential
ADS8330IB
DNL
LSB(2)
linearity
ADS8329I, ADS8330I
–1
±0.8
2
ADS8329IB,
– 0.5
±0.05
0.5
ADS8330IB
EO
Offset error(3)
mV
ADS8329I, ADS8330I
–0.8
±0.2
0.8
Offset error drift
FSR = 2.5 V
0.8
PPM/°C
EG
Gain error
– 0.25
–0.04
0.25
%FSR
Gain error drift
0.5
PPM/°C
At dc
70
CMRR
Common mode rejection ratio
dB
VI = 0.4 Vpp at 1 MHz
50
Noise
33
µV RMS
PSRR
Power supply rejection ratio
At FFFFh output code(3)
78
dB
SAMPLING DYNAMICS
tCONV
Conversion time
18
CCLK
tSAMPLE1
Manual trigger
3
Acquisition time
CCLK
tSAMPLE2
Auto trigger
3
Throughput rate
1
MHz
Aperture delay
5
ns
Aperture jitter
10
ps
Step response
100
ns
Overvoltage recovery
100
ns
(1)
Ideal input span, does not include gain or offset error.
(2)
LSB means least significant bit
(3)
Measured relative to an ideal full-scale input [+IN – (–IN)] of 2.5 V when +VA = 3 V.
5
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