HY57V161610D

Rev. 3.6/Apr.01

2

VSS

DQ15

DQ14

VSSQ

DQ13

DQ12

VDDQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VDDQ

NC

UDQM

CLK

CKE

NC

A9

A8

A7

A6

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

VSSQ

DQ6

DQ7

VDDQ

LDQM

WE

CAS

RAS

CS

A11

A10

A0

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

50 pin TSOP-II

400mil x 825mil

0.8mm pin pitch

A2

A3

VDD

A5

A4

VSS

23

24

25

28

27

26

P IN CONF IGURAT ION

P IN DESCR IPT ION

PIN

PIN NAME

DESCR IPTI ON

CLK

Clock

The system clock input. All other inputs are referenced to the SDRAM on the

rising edge of CLK.

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh.

CS

Chip Select

Command input enable or mask except CLK, CKE and DQM

BA

Bank Address

Select either one of banks during both RAS and CAS activity.

A0 ~ A10

Address

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

RAS , CAS , WE

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS , CAS and WE define the operation.

Refer function truth table for details

LDQM, UDQM

Data Input/Output Mask

DQM control output buffer in read mode and mask input data in write mode

DQ0 ~ DQ15

Data Input/Output

Multiplexed data input / output pin

Power Supply/Ground

Power supply for internal circuit and input buffer

Data Output Power/Ground

Power supply for DQ

NC

No Connection

No connection