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PZ3032I10A44 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PZ3032I10A44 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 14 page  Philips Semiconductors Product specification PZ3032 32 macrocell CPLD 1997 Feb 20 8 DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0 °C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT VIL Input voltage low VDD = 3.0V 0.8 V VIH Input voltage high VDD = 3.6V 2.0 V VI Input clamp voltage VDD = 3.0V, IIN = –18mA –1.2 V VOL Output voltage low VDD = 3.0V, IOL = 8mA 0.5 V VOH Output voltage high VDD = 3.0V, IOH = –8mA 2.4 V IIL Input leakage current low VDD = 3.6V (except CKO), VIN = 0V –10 10 µA IIH Input leakage current high VDD = 3.6V, VIN = 3.0V –10 10 µA IIL Clock input leakage current VDD = 3.6V, VIN = 0.4V –10 10 µA IOZL 3-Stated output leakage current low VDD = 3.6V, VIN = 0.4V –10 10 µA IOZH 3-Stated output leakage current high VDD = 3.6V, VIN = 3.0V –10 10 µA IDDQ Standby current VDD = 3.6V, Tamb = 0°C 35 µA IDDD1 Dynamic current VDD = 3.6V, Tamb = 0°C @ 1MHz 0.5 mA IDDD1 Dynamic current VDD = 3.6V, Tamb = 0°C @ 50MHz 18 mA IOS Short circuit output current 1 pin at a time for no longer than 1 second –5 –100 mA CIN Input pin capacitance Tamb = 25°C, f = 1MHz 8 pF CCLK Clock input capacitance Tamb = 25°C, f = 1MHz 5 12 pF CI/O I/O pin capacitance Tamb = 25°C, f = 1MHz 10 pF NOTE: 1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES Commercial: 0 °C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER –8 –10 –12 UNIT SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 8 2 10 2 12 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 10.5 3 13 3 15 ns tCO Clock to out delay time 2 7 2 9 2 11 ns tSU_PAL Setup time (from input or feedback node) through PAL 6.5 8.5 10.5 ns tSU_PLA Setup time (from input or feedback node) through PAL + PLA 9 11.5 13.5 ns tH Hold time 0 0 0 ns tCH Clock High time 3 4 5 ns tCL Clock Low time 3 4 5 ns tR Input rise time 20 20 20 ns tF Input fall time 20 20 20 ns fMAX1 Maximum FF toggle rate2 (1/tCH + tCL) 167 125 100 MHz fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF) 83 63 50 MHz fMAX3 Maximum external frequency2 (1/tSUPAL + tCO) 74 57 47 MHz tBUF Output buffer delay time 1.5 1.5 1.5 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 6.5 8.5 10.5 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA 9 11.5 13.5 ns tCF Clock to internal feedback node delay time 5.5 7.5 9.5 ns tINIT Delay from valid VDD to valid reset 50 50 50 µs tER Input to output disable3 15 17 19 ns tEA Input to output valid 15 17 19 ns tRP Input to register preset 16 18 20 ns tRR Input to register reset 19 21 23 ns NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. |
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