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PE97632 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. PE97632
Description  3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications
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Maker  ETC1 [List of Unclassifed Manufacturers]
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PE97632 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

 
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Advance Information
PE97632
Page 4 of 16
©2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0205-02
│ UltraCMOS™ RFIC Solutions
Pin No.
Pin
Name
Valid
Mode
Type
Description
47
Fin
Both
Input
Prescaler input from the VCO. 3.2 GHz max frequency.
48
Fin
Both
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50
Ω resistor directly to the ground plane.
49
GND
Downbond
Ground
50
CEXT
Both
Output
Logical “NAND” of PD_
U and PD_D terminated through an on chip, 2 k
Ω series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
51
LD
Both
Output
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
52
DOUT
Both
Output
Data out function, enabled in enhancement mode.
53
VDD
(Note 1)
Output driver/VDD.
54
GND
Downbond
Ground
55
PD_
D
Both
Output
PD_
D pulses down when f
p leads fc. PD_U is driven to GND when CPSEL = “High”.
56
NC
Both
No Connect
57
PD_
U
Both
Output
PD_
U pulses down when f
c leads fp. PD_D is driven to GND when CPSEL = “High”.
58
GND
Downbond
Ground
59
VDD
(Note 1)
Output driver/VDD.
60
VDD
(Note 1)
Phase detector VDD.
61
GND
Downbond
Ground
62
fr
Both
Input
Reference frequency input.
63
VDD
(Note 1)
Reference VDD.
64
VDD
(Note 1)
Digital core VDD.
GND
Downbond
Ground
65
ENH
Both
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
66
NC
Both
No Connect
67
MS2_SEL
Both
Input
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
68
RND_SEL
Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 219.
Note 1:
All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
All digital input pins have 70 k
Ω pull-down resistors to ground.
46
VDD
(Note 1)
Prescaler VDD.


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