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56F8037 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

Part No. 56F8037
Description  16-bit Digital Signal Controllers
Download  180 Pages
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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56F8037 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc

 
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56F8037 Data Sheet, Rev. 2
4
Freescale Semiconductor
Preliminary
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8037 Features . . . . . . . . . . . . . . . . . . . . . 5
1.2. 56F8037 Description . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . . 8
1.4. Architecture Block Diagram . . . . . . . . . . . . . . 8
1.5. Product Documentation . . . . . . . . . . . . . . . 16
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 16
Part 2: Signal/Connection Descriptions . . . 17
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. 56F8037 Signal Pins . . . . . . . . . . . . . . . . . 22
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . 39
3.4. Internal Clock Source . . . . . . . . . . . . . . . . . 40
3.5. Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . 40
3.6. Ceramic Resonator. . . . . . . . . . . . . . . . . . . 41
3.7. External Clock Input - Crystal
Oscillator Option . . . . . . . . . . . . . . 41
3.8. Alternate External Clock Input . . . . . . . . . . . 42
Part 4: Memory Maps . . . . . . . . . . . . . . . . . 42
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.3. Program Map . . . . . . . . . . . . . . . . . . . . . . . 45
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. EOnCE Memory Map . . . . . . . . . . . . . . . . . 46
4.6. Peripheral Memory-Mapped Registers . . . . 47
Part 5: Interrupt Controller (ITCN) . . . . . . . . 64
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3. Functional Description . . . . . . . . . . . . . . . . 64
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 66
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 67
5.6. Register Descriptions . . . . . . . . . . . . . . . . . . 67
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Part 6: System Integration Module (SIM). . 89
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3. Register Descriptions . . . . . . . . . . . . . . . . . 91
6.4. Clock Generation Overview . . . . . . . . . . . 120
6.5. Power-Saving Modes . . . . . . . . . . . . . . . . . 120
6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.7. Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 125
Part 7: Security Features . . . . . . . . . . . . . . 125
7.1. Operation with Security Enabled . . . . . . . . 125
7.2. Flash Access Lock and Unlock
Mechanisms . . . . . . . . . . . . . . . . 126
Part 8: General Purpose Input/Output (GPIO)
127
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 127
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 127
8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . 131
Part 9: Joint Test Action Group (JTAG) . . 136
9.1. 56F8037 Information . . . . . . . . . . . . . . . . . 136
Part 10: Specifications. . . . . . . . . . . . . . . . 136
10.1. General Characteristics . . . . . . . . . . . . . . 136
10.2. DC Electrical Characteristics . . . . . . . . . . 140
10.3. AC Electrical Characteristics . . . . . . . . . . 143
10.4. Flash Memory Characteristics . . . . . . . . . 143
10.5. External Clock Operation Timing . . . . . . . 144
10.6. Phase Locked Loop Timing . . . . . . . . . . . 145
10.7. Relaxation Oscillator Timing . . . . . . . . . . 145
10.8. Reset, Stop, Wait, Mode Select,
and Interrupt Timing . . . . . . . . . . 147
10.9. Serial Peripheral Interface (SPI) Timing . 148
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . 151
10.11. Queued Serial Communication
Interface (QSCI) Timing . . . . . . . . 152
10.12. Freescale’s Scalable Controller Area
Network (MSCAN) Timing . . . . . . 153
10.13. Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 153
10.14. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 155
10.15. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 156
10.16. Equivalent Circuit for ADC Inputs . . . . . . 157
10.17. Comparator (CMP) Parameters . . . . . . . 157
10.18. Digital-to-Analog Converter (DAC)
Parameters . . . . . . . . . . . . . . . . . 158
10.19. Power Consumption . . . . . . . . . . . . . . . . 159
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 161
11.1. 56F8037 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 161
Part 12: Design Considerations . . . . . . . . 164
12.1. Thermal Design Considerations . . . . . . . . 164
12.2. Electrical Design Considerations . . . . . . . 165
Part 13: Ordering Information . . . . . . . . . . 166
Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 167
56F8037 Data Sheet Table of Contents


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