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MAX5953A Datasheet(PDF) 6 Page - Maxim Integrated Products

Part No. MAX5953A
Description  IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX5953A Datasheet(HTML) 6 Page - Maxim Integrated Products

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IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT =
100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at
TJ = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT (DCUVLO)
Threshold Voltage
VREF,DCUVLO
VDCUVLO rising
1.14
1.26
1.38
V
Hysteresis
VHYS,DCUVLO
140
mV
Input Bias Current
IIN,DCUVLO
VDCUVLO = 3V
-100
+100
nA
SUPPLY CURRENT
From VHVIN = 11V to 76V,
VCSS = 0V, VINBIAS = 11V
0.7
1.5
From VINBIAS = 11V to 76V,
VCSS = 0V, VHVIN = 76V
4.4
6.4
Supply Current
From VHVIN = 76V, VOPIO = 4V
7
mA
Standby Supply Current
VDCUVLO = 0V
1
mA
Note 1:
Limits at 0°C are guaranteed by design, unless otherwise noted.
Note 2:
The input offset current is illustrated in Figure 1.
Note 3:
Effective differential input resistance is defined as the differential resistance between V+ and VEE without any external
resistance.
Note 4:
Classification current is turned off whenever the IC is in power mode.
Note 5:
See Table 2 in the Classification Mode section. RDISC and RRCLASS must be 1%, 100ppm or better. ICLASS includes the IC
bias current and the current drawn by RDISC.
Note 6:
See the Thermal Dissipation section.
Note 7:
When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on UVLO does
not exceed its maximum rating of 8V when VIN is at the maximum voltage.
Note 8:
When VUVLO is below VTH,G,UVLO, the MAX5953A/MAX5953C set the turn-on voltage threshold internally (VUVLO,ON).
Note 9:
An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the
MAX5953A/MAX5953B/MAX5953C/MAX5953D to exit power-on mode (as long as the input voltage remains above an
operable voltage level of 12V).
Note 10: Guaranteed by design, not tested in production for MAX5953B/MAX5953D.
Note 11: PGOOD references to OUT while PGOOD references to VEE.
Note 12: Output switching frequency is 1/2 oscillator frequency.
Figure 1. Effective Differential Input Resistance/Offset Current
IIN
IINi + 1
IINi
IOFFSET
dRi
1V
VINi
VINi + 1
IOFFSET ≅ IINi -
VINi
dRi
dRi
(VINi + 1 - VINi)
=
1V
(IINi + 1 - IINi)
(IINi + 1 - IINi)
VIN


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