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ISL6322 Datasheet(PDF) 23 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6322 Datasheet(HTML) 23 Page - Intersil Corporation

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23
FN6328.0
August 21, 2006
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from the following equation:
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. The
ΔVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
Gate Drive Voltage Versatility
The ISL6322 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC and the VID pins. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, the controller asserts
PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met, for both Intel and
AMD modes of operation, before the ISL6322 is released
from shutdown mode to begin the soft-start startup
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6322 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6322 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical Specifications
on page 7).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6322 in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
3. The voltage on the EN_PH4 pin must be above 1.21V.
The EN_PH4 input allows for power sequencing between
the controller and the external driver.
4. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6322 to begin operation, PVCC1 is the
only pin that is required to have a voltage applied that
exceeds POR. However, for 2 or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6322 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see Electrical Specifications on page 7).
For Intel VR10, VR11 and AMD 6-bit modes of operation
these are the only conditions that must be met for the
controller to immediately begin the soft-start sequence. If
running in AMD 5-bit mode of operation there is one more
condition that must be met:
C
BOOT_CAP
Q
GATE
ΔV
BOOT_CAP
--------------------------------------
Q
GATE
Q
G1 PV CC
V
GS1
---------------------------------- N
Q1
=
(EQ. 16)
50nC
20nC
FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
ΔVBOOT_CAP (V)
1.6
1.4
1.2
1.
0.8
0.6
0.4
0.2
0.0
0.3
0.0
0.1
0.2
0.4
0.5
0.6
0.9
0.7
0.8
1.0
QGATE = 100nC
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
EXTERNAL CIRCUIT
ISL6322 INTERNAL CIRCUIT
-
+
0.85V
EN
+12V
POR
CIRCUIT
10.7k
Ω
1.40k
Ω
ENABLE
COMPARATOR
SOFT-START
AND
FAULT LOGIC
VCC
PVCC1
EN_PH4
-
+
1.21V
ISL6322


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