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ISL6322 Datasheet(PDF) 21 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 21 Page - Intersil Corporation

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21
FN6328.0
August 21, 2006
resistor, N is the active channel number, and DCR is the
Inductor DCR value.
Therefore the equivalent load-line impedance, i.e. droop
impedance, is equal to:
Output-Voltage Offset Programming
The ISL6322 allows the designer to accurately adjust the
offset voltage by connecting a resistor, ROFS, from the OFS
pin to VCC or GND. When ROFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into the FB pin
and out of the OFS pin. If ROFS is connected to ground, the
voltage across it is regulated to 0.4V, and IOFS flows into the
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(IOFS x RFB). These functions are shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Negative Offset (connect ROFS to GND):
For Positive Offset (connect ROFS to VCC):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6322
to do this by making changes to the VID inputs. The ISL6322
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6322 is operating in
determines how the controller responds to a dynamic VID
change.
Intel Dynamic VID Transitions
When in Intel VR10 or VR11 mode, the ISL6322 checks the
VID inputs on the positive edge of an internal 3MHz clock. If
a new code is established and it remains stable for 3
consecutive readings (1
μs to 1.33μs), the ISL6322
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VR10 and VR11 settings, the ISL6322 will immediately
change the internal DAC reference to the new requested
value as soon as the request is validated, which means the
fastest recommended rate at which a bit change can occur is
once every 2
μs. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1k
Ω resistor between the DAC and the REF pin,
and the external capacitor CREF, between the REF pin and
R
LL
R
FB
N
------------
DCR
R
ISEN
------------------
=
(EQ. 11)
(EQ. 12)
R
OFS
0.4 R
FB
V
OFFSET
--------------------------
=
(EQ. 13)
R
OFS
1.6 R
FB
V
OFFSET
--------------------------
=
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
E/A
FB
OFS
VCC
+
1.6V
VCC
ROFS
RFB
VDIFF
ISL6322
REF
VOFS
+
-
IOFS
IOFS
1:1
CURRENT
MIRROR
-
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
E/A
FB
OFS
GND
+
0.4V
ROFS
RFB
VDIFF
ISL6322
REF
VOFS
+
-
IOFS
IOFS
1:1
CURRENT
MIRROR
VCC
-
GND
ISL6322


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