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ISL6322 Datasheet(PDF) 20 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 20 Page - Intersil Corporation

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20
FN6328.0
August 21, 2006
Voltage Regulation
The integrating compensation network shown in Figure 6
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6322 to include the
combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to the
triangle waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 8. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
The ISL6322 incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, VDIFF, is
connected to the inverting input of the error amplifier through
an external resistor.
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, IAVG, flows from FB through a
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equation 9 with Equation 10.
In Equation 10, VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the internal sense resistor
connected to the ISEN+ pin, and RFB is the feedback
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
TABLE 5. AMD 6-BIT VOLTAGE IDENTIFICATION CODES
(Continued)
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
V
OUT
V
REF
V
OFS
V
DROOP
=
(EQ. 8)
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
IAVG
EXTERNAL CIRCUIT
ISL6322 INTERNAL CIRCUIT
COMP
RC
RFB
FB
VDIFF
VSEN
RGND
-
+
(VDROOP + VOFS)
ERROR
-
+
VOUT+
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
VCOMP
CC
REF
CREF
-
+
VOUT-
IDROOP
VID DAC
1k
AMPLIFIER
IOFS
V
DROOP
I
AVG
R
FB
=
(EQ. 9)
V
OUT
V
REF
V
OFS
I
OUT
N
-------------
DCR
R
ISEN
------------------
R
FB
⋅⋅
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 10)
ISL6322


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