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ISL6322 Datasheet(PDF) 37 Page  Intersil Corporation 

ISL6322 Datasheet(HTML) 37 Page  Intersil Corporation 
37 / 41 page 37 FN6328.0 August 21, 2006 The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔVMAX. Most capacitor solutions rely on a mixture of highfrequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited highfrequency performance. Minimizing the ESL of the highfrequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the outputvoltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see “Interleaving” on page 11 and Equation 2), a voltage develops across the bulk capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance. Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔV MAX. This places an upper limit on inductance. Equation 45 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater outputvoltage deviation than the leading edge. Equation 46 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation: L is the perchannel inductance, C is the total output capacitance, and N is the number of active channels. Switching Frequency There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output voltage ripple as outlined in “Compensation without Load line Regulation” on page 35. Choose the lowest switching frequency that allows the regulator to meet the transient response requirements. Switching frequency is determined by the selection of the frequencysetting resistor, RT. Figure 25 and Equation 47 are provided to assist in selecting the correct value for RT. Input Capacitor Selection The input capacitors are responsible for sourcing the ac component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the ac component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. L ESR V IN NV ⋅ OUT – ⎝⎠ ⎛⎞ V OUT ⋅ f S VIN VPP MAX () ⋅⋅  ⋅ ≥ (EQ. 44) L 2NCVO ⋅⋅⋅ ΔI ()2  ΔV MAX ΔIESR ⋅ () – ⋅ ≤ (EQ. 45) L 1.25 NC ⋅⋅ ΔI ()2  ΔV MAX ΔI ESR ⋅ () – V IN V O – ⎝⎠ ⎛⎞ ⋅⋅ ≤ (EQ. 46) R T 10 10.61 1.035 fS () log ⋅ () – [] = (EQ. 47) 10 100 1000 10 100 1000 10000 FIGURE 25. RT vs SWITCHING FREQUENCY SWITCHING FREQUENCY (kHz) FIGURE 26. NORMALIZED INPUTCAPACITOR RMS CURRENT vs DUTY CYCLE FOR 4PHASE CONVERTER 00.4 1.0 0.2 0.6 0.8 DUTY CYCLE (VO/VIN) 0.3 0.1 0 0.2 IL,PP = 0 IL,PP = 0.25 IO IL,PP = 0.5 IO IL,PP = 0.75 IO ISL6322 
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