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ISL6322 Datasheet(PDF) 36 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 36 Page - Intersil Corporation

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36
FN6328.0
August 21, 2006
type III controller, as shown in Figure 24, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, fHF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose fHF = 10f0, but it can be
higher if desired. Choosing fHF to be lower than 10f0 can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 42, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 42.
In Equation 42, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the
peak-to-peak sawtooth signal amplitude as described in
Electrical Specifications on page 7.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step,
ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading,
ΔV
MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by the amount
specified in Equation 43.
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
ISL6322
COMP
CC
RC
RFB
FB
IDROOP
VDIFF
C2
C1
R1
C
C
0.75 V
IN
2
π f
HF
LC
1
⋅⋅
()
⋅⋅
2
π
()2 f
0 fHF
LC
() R
FB VPP
⋅⋅
----------------------------------------------------------------------------------------------------
=
R
C
V
PP
2
π
⎝⎠
⎛⎞
2
f
0 fHF LCRFB
⋅⋅
⋅ ⋅ ⋅
0.75 V
IN
2
π f
HF
LC
1
⋅⋅
()
⋅⋅
-----------------------------------------------------------------------------------------
=
R
1
R
FB
CESR
LC
C ESR
--------------------------------------------
=
C
1
LC
C ESR
R
FB
--------------------------------------------
=
C
2
0.75 V
IN
2
π
()2 f
0 fHF
LC
() R
FB VPP
⋅⋅
----------------------------------------------------------------------------------------------------
=
(EQ. 42)
ΔVESL di
dt
-----
ESR
ΔI
+
(EQ. 43)
ISL6322


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