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ISL6322 Datasheet(PDF) 35 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
Download  41 Pages
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 35 Page - Intersil Corporation

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35
FN6328.0
August 21, 2006
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in “Load-Line (Droop) Regulation” on page 20,
there are two distinct methods for achieving these goals:
“Compensation with Load-line Regulation” on page 35 and
“Compensation without Load-line Regulation” on page 35.
Compensation with Load-line Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 41:
- L is the per-channel filter inductance divided by the
number of active channels,
- C is the sum total of all output capacitors,
- ESR is the equivalent series resistance of the bulk output
filter capacitance, and
-VPP is the peak-to-peak sawtooth signal amplitude as
described in the Electrical Specifications on page 7.
Once selected, the compensation values in Equation 41
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from the
case equations in Equation 41 unless some performance
issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 23). Keep
a position available for C2, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Compensation without Load-line Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6322 CIRCUIT
ISL6322
COMP
CC
RC
RFB
FB
VDIFF
C2 (OPTIONAL)
IDROOP
1
2
π
LC
⋅⋅
--------------------------------f
0
>
R
C
R
FB
2
π f
0 Vpp
LC
⋅⋅
0.66 V
IN
--------------------------------------------------------
=
C
C
0.66 V
IN
2
π V
PP RFB f0
⋅⋅
----------------------------------------------------
=
Case 1:
1
2
π
LC
⋅⋅
--------------------------------
f
0
1
2
π C ESR
⋅⋅ ⋅
-------------------------------------
<
R
C
R
FB
V
PP
2
π
()
2
f
0
2
LC
⋅⋅ ⋅
0.66
V
IN
-----------------------------------------------------------------
=
C
C
0.66 V
IN
2
π
()2 f
0
2
V
PP RFB
LC
⋅⋅
-------------------------------------------------------------------------------------
=
Case 2:
(EQ. 41)
f
0
1
2
π C ESR
⋅⋅ ⋅
-------------------------------------
>
R
C
R
FB
2
π f
0 Vpp L
⋅⋅
0.66
V
IN ESR
⋅⋅
---------------------------------------------
=
C
C
0.66 V
IN ESR
C
⋅⋅
2
π V
PP RFB f0
L
⋅⋅
----------------------------------------------------------------
=
Case 3:
ISL6322


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