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ISL6322 Datasheet(PDF) 33 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 33 Page - Intersil Corporation

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33
FN6328.0
August 21, 2006
quiescent current with no load at both drive outputs; NQ1
and NQ2 are the number of upper and lower MOSFETs per
phase, respectively; NPHASE is the number of active
phases. The IQ*VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, PDR_UP, the lower drive path resistance,
PDR_UP, and in the boot strap diode, PBOOT. The rest of the
power will be dissipated by the external gate resistors (RG1
and RG2) and the internal gate resistors (RGI1 and RGI2) of
the MOSFETs. Figures 19 and 20 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, PDR, can be roughly
estimated with Equation 31.
Inductor DCR Current Sensing Component
Selection
The ISL6322 senses each individual channel’s inductor
current by detecting the voltage across the output inductor
DCR of that channel (as described in “Continuous Current
Sampling” on page 13). As Figure 21 illustrates, an R-C
network is required to accurately sense the inductor DCR
voltage and convert this information into a current, which is
proportional to the total output current. The time constant of
this R-C network must match the time constant of the
inductor L/DCR.
The R-C network across the inductor also sets the
overcurrent trip threshold for the regulator. Before the R-C
components can be selected, the desired overcurrent
protection level should be chosen. The minimum overcurrent
trip threshold the controller can support is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, IOCP,min, use
Equation 32, where N is the number of active channels, and
DCR is the individual inductor’s DCR.
The overcurrent trip level of the ISL6322 cannot be set any
lower then the IOCP,min level calculated above. If the
minimum overcurrent trip level is desired, do the
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q1
D
S
G
RGI1
RG1
BOOT
RHI1
CDS
CGS
CGD
RLO1
PHASE
PVCC
UGATE
PVCC
Q2
D
S
G
RGI2
RG2
RHI2
CDS
CGS
CGD
RLO2
LGATE
P
DR
P
DR_UP
P
DR_LOW
P
BOOT
I
Q VCC
()
++
+
=
(EQ. 31)
P
DR_UP
R
HI1
R
HI1
R
EXT1
+
--------------------------------------
R
LO1
R
LO1
R
EXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞ P
Qg_Q1
3
---------------------
=
P
DR_LOW
R
HI2
R
HI2
R
EXT2
+
--------------------------------------
R
LO2
R
LO2
R
EXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞ P
Qg_Q2
2
---------------------
=
R
EXT1
R
G1
R
GI1
N
Q1
-------------
+
=
R
EXT2
R
G2
R
GI2
N
Q2
-------------
+
=
P
BOOT
P
Qg_Q1
3
---------------------
=
FIGURE 21. DCR SENSING CONFIGURATION
In
-
+
ISEN-(n)
SAMPLE
ISL6322 INTERNAL CIRCUIT
VIN
UGATE(n)
RISEN
DCR
L
INDUCTOR
R1
VOUT
COUT
VC(s)
C1
I
L
VL(s)
ISEN
R2*
VC(s)
*R2 is OPTIONAL
ISEN+(n)
LGATE(n)
MOSFET
DRIVER
I
OCP min
,
0.0375 N
DCR
---------------------------
=
(EQ. 32)
ISL6322


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