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ISL6322 Datasheet(PDF) 32 Page  Intersil Corporation 

ISL6322 Datasheet(HTML) 32 Page  Intersil Corporation 
32 / 41 page 32 FN6328.0 August 21, 2006 An additional term can be added to the lowerMOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lowerMOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON), the switching frequency, fS, and the length of dead times, td1 and td2, at the beginning and the end of the lowerMOSFET conduction interval respectively. The total maximum power dissipated in each lower MOSFET is approximated by the summation of PLOW,1 and PLOW,2. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upperMOSFET losses are dependent on switching frequency, the power calculation is more complex. Upper MOSFET losses can be divided into separate components involving the upperMOSFET switching times, the lowerMOSFET bodydiode reverserecovery charge, Qrr, and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 25, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 26, the approximate power loss is PUP,2. A third component involves the lower MOSFET reverserecovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lowerMOSFET body diode can recover all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3. Finally, the resistive part of the upper MOSFET is given in Equation 28 as PUP,4. The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 25, 26, 27 and 28. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. Package Power Dissipation When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of three drivers in the controller package, the total power dissipated by all three drivers must be less than the maximum allowable power dissipation for the QFN package. Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125°C. The maximum allowable IC power dissipation for the 7x7 QFN package is approximately 3.5W at room temperature. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the ISL6322 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, PQg_TOT, due to the gate charge of MOSFETs and the integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 29 and 30, respectively. In Equations 29 and 30, PQg_Q1 is the total upper gate drive power loss and PQg_Q2 is the total lower gate drive power loss; the gate charge (QG1 and QG2) is defined at the particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; IQ is the driver total (EQ. 24) P LOW 2 , V DON () fS I M N  IPP 2  + ⎝⎠ ⎜⎟ ⎛⎞ t d1 ⋅ I M N  I PP 2  – ⎝⎠ ⎜⎟ ⎜⎟ ⎛⎞ t d2 ⋅ + ⋅⋅ = (EQ. 25) P UP 1 , V IN I M N  I PP 2  + ⎝⎠ ⎛⎞ t 1 2  ⎝⎠ ⎜⎟ ⎛⎞ f S ⋅⋅ ⋅ ≈ P UP 2 , V IN I M N  I PP 2  – ⎝⎠ ⎜⎟ ⎛⎞ t 2 2  ⎝⎠ ⎜⎟ ⎛⎞ f S ⋅⋅ ⋅ ≈ (EQ. 26) P UP 3 , V IN Q rr f S ⋅⋅ = (EQ. 27) P UP 4 , r DS ON () I M N  ⎝⎠ ⎜⎟ ⎛⎞ 2 d ⋅ I PP 2 12  + ⋅ ≈ (EQ. 28) P Qg_TOT P Qg_Q1 P Qg_Q2 I Q VCC ⋅ ++ = (EQ. 29) P Qg_Q1 3 2  Q G1 PVCC FSW NQ1 NPHASE ⋅⋅ ⋅ ⋅ ⋅ = P Qg_Q2 Q G2 PVCC FSW NQ2 NPHASE ⋅⋅ ⋅ ⋅ = I DR 3 2  Q G1 N ⋅ Q1 ⋅ Q G2 NQ2 ⋅ + ⎝⎠ ⎛⎞ N PHASE FSW I Q + ⋅⋅ = (EQ. 30) ISL6322 
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