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ISL6322 Datasheet(PDF) 28 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 28 Page - Intersil Corporation

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28
FN6328.0
August 21, 2006
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB) and the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9 clock pulses.
The ninth pulse is the acknowledge bit (A). After the start
condition, the master sends 7 slave address bits and a R/W
bit during the next 8 clock pulses. During the ninth clock
pulse, the device that recognizes its own address holds the
data line low to acknowledge. The acknowledge bit is also
used by both the master and the slave to acknowledge
receipt of register addresses and data as described below.
ISL6322 I2C Slave Address
All devices on the I2C bus must have a 7-bit I2C address in
order to be recognized. The ISL6322 has two user
selectable addresses to ensure it does not interfere with
other devices on the bus. The address is programmed via
the Rss resistor on the SS/RST/A0 pin. Placing the Rss
resistor from the SS/RST/A0 pin to ground sets the I2C
address to be 1000_110. If the Rss resistor is placed from
the SS/RST/A0 pin to VCC the address is 1000_111.
Please note that the I2C address of the ISL6322 is
programmed from the SS/RST/A0 pin as soon as VCC rises
above the POR threshold. The ISL6322’s I2C address stays
the same and can not be reprogrammed until VCC falls back
below the POR falling threshold.
Communicating Over the I2C Bus
Two transactions are supported on the I2C interface: 1) Write
register, 2) Read register from current address.
All transactions start with a control byte sent from the I2C
master device. The control byte begins with a Start condition,
followed by 7-bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write or 1 for a read. If
any slaves on the I2C bus recognize their address, they will
Acknowledge by pulling the serial data line low for the last
clock cycle in the control byte. If no slaves exist at that
address or are not ready to communicate, the data line will
be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL6322
acknowledges it, the 2nd byte sent by the master must be a
register address byte. This register address byte tells the
ISL6322 which one of the two internal registers it wants to
write to or read from. The address of the first internal
register, RGS1, is 0000_0000. This register sets the Voltage
Margining Offset. The address of the second internal
register, RGS2, is 0000_0001. This register sets the
Adaptive Deadtime Control, Overvoltage Protection, and
Switching Frequency parameters. Once the ISL6322 receives
a correct register address byte, it responds with an
acknowledge.
Writing to the Internal Registers
In order to change any of the four operating parameters via
the I2C bus, the internal registers must be written to. The two
registers inside the ISL6322 can be written individually with
two separate write transactions or sequentially with one write
transaction by sending two data bytes as described below.
To write to a single register in the ISL6322, the master sends
a control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL6322, it sends a
register address byte representing the internal register it
wants to write to (0000_0000 for RGS1 or 0000_0001 for
RGS2). The ISL6322 will respond with an Acknowledge. The
master then sends a byte representing the data byte to be
written into the desired register. The ISL6322 will respond
with an Acknowledge. The master then issues a Stop
condition, indicating to the ISL6322 that the current
transaction is complete. Once this transaction completes,
the ISL6322 will immediately update and change the
operating parameters on-the-fly.
It is also possible to write to both registers sequentially. To
do this the master must write to register RGS1 first. This
transaction begins with the master sending a control byte
with the R/W bit set to 0. If it receives an Acknowledge from
the ISL6322, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6322 will
respond with an Acknowledge. After sending the data byte to
SDA
SCL
START
CONDITION
FIGURE 17. START AND STOP WAVEFORMS
STOP
CONDITION
SP
SDA
SCL
FIGURE 18. ACKNOWLEDGE ON THE I2C BUS
1
2
8
9
ACKNOWLEDGE
FROM SLAVE
MSB
START
ISL6322


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