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ISL6322 Datasheet(PDF) 27 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 27 Page - Intersil Corporation

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27
FN6328.0
August 21, 2006
continue indefinitely until either the controller is disabled or
the fault is cleared. Note that the energy delivered during
trip-retry cycling is much less than during full-load operation,
so there is no thermal hazard.
Individual Channel Overcurrent Limiting
The ISL6322 has the ability to limit the current in each
individual channel without shutting down the entire regulator.
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170
μA OCL
reference current as shown in Figure 14. If a channel’s
individual sensed current exceeds this OCL limit, the UGATE
signal of that channel is immediately forced low, and the
LGATE signal is forced high. This turns off the upper
MOSFET(s), turns on the lower MOSFET(s), and stops the
rise of current in that channel, forcing the current in the
channel to decrease. That channel’s UGATE signal will not
be able to return high until the sensed channel current falls
back below the 170
μA reference.
I2C Bus Interface
The ISL6322 includes an I2C bus interface which allows for
user programmability of four of the controller’s operating
parameters. The operating parameters that can be adjusted
through the I2C are:
1. Voltage Margining Offset: The output voltage can be
positively offset up to +787.5mV in 12.5mV increments.
2. Adaptive Deadtime Control: Selects between LGATE
Detect and PHASE Detect deadtime control schemes as
described in the User Selectable Adaptive Deadtime
Control Techniques section.
3. Overvoltage Trip Level: Selects the overvoltage
protection trip threshold as described in the Overvoltage
Protection section.
4. Switching Frequency: The switching frequency can be
increased by a fixed +15% or +30%, or can be decreased
by -15% or -30%.
To adjust these four parameters, data transmission from the
main microprocessor to the ISL6322 and vice versa must take
place through the two wire I2C bus interface. The two wires of
the I2C bus consist of the SDA line, over which all data is sent,
and the SCL line, which is a clock signal used to synchronize
sending/receiving of the data.
Both SDA and SCL are bidirectional lines, externally connected
to a positive supply voltage via a pull-up resistor. Pull-up
resistor values should be chosen to limit the input current to
less then 3mA
. When the bus is free, both lines are HIGH. The
output stages of ISL6322 have an open drain/open collector in
order to perform the wired-AND function. Data on the I2C bus
can be transferred up to 100Kbps in the standard-mode or up to
400Kbps in the fast-mode. The level of logic “0” and logic “1” is
dependent on associated value of VDD as per electrical
specification table. One clock pulse is generated for each data
bit transferred. The ISL6322 is a “SLAVE only” device, so the
SCL line must always be controlled by an external master.
It is important to note that the I2C interface of the ISL6322
only works once the voltage on the VCC pin has risen above
the POR rising threshold. The I2C will continue to remain
active until the voltage on the VCC pin falls back below the
falling POR threshold level.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 16.
START and STOP Conditions
As shown in Figure 17, a START (S) condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
0A
0V
3ms/DIV
OUTPUT CURRENT, 50A/DIV
FIGURE 15. OVERCURRENT BEHAVIOR IN HICCUP MODE
OUTPUT VOLTAGE,
500mV/DIV
SDA
SCL
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
FIGURE 16. DATA VALIDITY
ISL6322


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