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ISL6322 Datasheet(PDF) 26 Page - Intersil Corporation

Part No. ISL6322
Description  Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6322 Datasheet(HTML) 26 Page - Intersil Corporation

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26
FN6328.0
August 21, 2006
in. Table 6 and 7 below list what the OVP trip levels are under
all conditions (see pages 27 through 31 for details of
controlling OVP thresholds with I2C).
At the inception of an overvoltage event, LGATE1, LGATE2
and LGATE3 are commanded high, PWM4 is commanded
low, and the PGOOD signal is driven low. This turns on the
all of the lower MOSFETs and pulls the output voltage below
a level that might cause damage to the load. The LGATE
outputs remain high and PWM4 remains low until VDIFF falls
100mV below the OVP threshold that tripped the overvoltage
protection circuitry. The ISL6322 will continue to protect the
load in this fashion as long as the overvoltage condition
recurs.
Once an overvoltage condition ends, the ISL6322 latches off
and must be reset by toggling EN, or through POR, before a
soft-start can be re-initiated.
One exception that overrides the overvoltage protection
circuitry is a dynamic VID transition in AMD modes of
operation. If a new VID code is detected during normal
operation, the OVP protection circuitry is disabled from the
beginning of the dynamic VID transition, until 50
μs after the
internal DAC reaches the final VID setting. This is the only
time during operation of the ISL6322 that the OVP circuitry is
not active.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6322 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10k
Ω resistor tied from PHASE to LGATE, which
turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6322 is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VDIFF and
RGND pins. In the event of an open sense line fault, the
controller will continue to remain off until the fault goes away,
at which point the controller will re-initiate a soft-start
sequence.
Overcurrent Protection
The ISL6322 takes advantage of the proportionality between
the load current and the average current, IAVG, to detect an
overcurrent condition. See “Continuous Current Sampling”
on page 13 for more detail on how the average current is
measured. The average current is continually compared with
a constant 125
μA OCP reference current as shown in
Figure 14. Once the average current exceeds the OCP
reference current, a comparator triggers the converter to
begin overcurrent protection procedures.
This method for detecting overcurrent events limits the
minimum overcurrent trip threshold because of the fact the
ISL6322 uses set internal RISEN current sense resistors.
The minimum overcurrent trip threshold is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, IOCP,min, use
Equation 21, where N is the number of active channels, DCR
is the individual inductor’s DCR, and RISEN is the 300Ω
internal current sense resistor. If the desired overcurrent trip
level is greater then the minimum overcurrent trip level,
IOCP,min, then the resistor divider R-C circuit around the
inductor shown in Figure 5 should be used to set the desired
trip level.
The overcurrent trip level of the ISL6322 cannot be set any
lower than the IOCP,min level calculated above.
At the beginning of overcurrent shutdown, the controller sets
all of the UGATE and LGATE signals low, puts PWM4 in a
high-impedance state, and forces PGOOD low. This turns off
all of the upper and lower MOSFETs. The system remains in
this state for a fixed period of 12ms. If the controller is still
enabled at the end of this wait period, it will attempt a
soft-start. If the fault remains, the trip-retry cycles will
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
MODE OF
OPERATION
DEFAULT
ALTERNATE
Soft-Start
(TD1 and TD2)
1.280V and
VDAC+250mV
(higher of the two)
1.280V and
VDAC+175mV
(higher of the two)
Soft-Start
(TD3 and TD4)
VDAC+250mV
VDAC+175mV
Normal Operation
VDAC+250mV
VDAC+175mV
TABLE 7. AMD OVP THRESHOLDS
MODE OF
OPERATION
DEFAULT
ALTERNATE
Soft-Start
2.200V and
VDAC+250mV
(higher of the two)
2.200V and
VDAC+175mV
(higher of the two)
Normal Operation
VDAC+250mV
VDAC+175mV
I
OCP min
,
125 10
6
R
ISEN N
⋅⋅
DCR
----------------------------------------------------------
=
(EQ. 21)
(EQ. 22)
I
OCP
I
OCP min
,
>
I
OCP
125 10
6
R
ISEN N
⋅⋅
DCR
----------------------------------------------------------
⎝⎠
⎜⎟
⎛⎞
R
1
R
2
+
R
2
---------------------
⎝⎠
⎜⎟
⎛⎞
=
ISL6322


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