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STSMIA832 Datasheet(PDF) 6 Page - STMicroelectronics

Part No. STSMIA832
Description  1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STSMIA832 Datasheet(HTML) 6 Page - STMicroelectronics

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Pin configuration
Both the Camera Sensor module and the Baseband processor interface operate at VL =
1.8V. The subLVDS receiver core operating voltage is VDD = 2.8V typical.
Supplementary notes: SMIA specification
The Standard Mobile Imaging Architecture (SMIA) specification defines an interface
between the digital camera module and mobile phone engine. It defines a standard data
transmission and control interface between transmitter (camera module) and receiver
(mobile phone engine). The data transmission interface (referred to as CCP2) is a
unidirectional differential serial interface with data and clock/strobe signals. The physical
layer of CCP2 is based on signaling scheme called SubLVDS, which is current mode
differential low voltage signaling method modified from the IEEE 1596.3 LVDS standard for
reduced power consumption. STSMIA832 operates in a data/strobe signaling mode. The
use of data-strobe coding together with SubLVDS enables the use of high data rates with
low EMI.
Data/Clock signaling
Data is a differential output from camera module. Data format is in most of cases bytewise
(i.e. on 8-bit boundary) least significant bit (LSB) first. When nothing is being transferred, the
DATA lines remain high, except in power shutdown. Figure illustrates the bytewise LSB first
Clock is a differential signal, output from camera module. The receiver reads the data on
rising edge of the CCP_CLK. The clock signal may be free running or gated. For most cases
free running clock is preferred due to simpler implementation in the transmitting end.
However, in some cases gated clock may be better solution. If gated transmission clock is
used, clock remains high when nothing is being transferred, except in power shutdown.
Data/Strobe signaling
The data-strobe coding consists of two parallel signals, data and strobe. The data signal
carries the bit-serial data while the strobe signal state toggles whenever data signal does
not change state. Thus, either the data signal or the strobe signal changes between two
data bits. If both signals change simultaneously it is interpreted as an error. The signaling
method is presented in the figure 2 below.
The benefit of using data-strobe signaling is that there is no need for transferring continuous
clock over the CCP2 bus. The frequency of the bus is also divided by two. The clock is
reconstructed at the receiving end from the data and strobe signals. This simplifies the EMC
design and in addition, EMI is reduced compared to normal data/clock signaling.
Figure 4.
Data clock signaling

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