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DS2167Q Datasheet(PDF) 2 Page - Dallas Semiconductor |
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DS2167Q Datasheet(HTML) 2 Page - Dallas Semiconductor |
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2 / 15 page  DS2167/DS2168 022698 2/15 PRODUCT OVERVIEW The DS2167 and DS2168 contain three major function- al blocks: a high performance (10 MIPS) DSP “engine,” two independent PCM data interfaces (“X” and “Y”) which connect directly to serial time division multiplexed (TDM) backplanes and a microcontroller-compatible serial port for on-the-fly device configuration. A 10MHz master clock is required by the DSP engine. The de- vices’ dual channel architecture supports full duplex, dual compression or dual expansion operation. The PCM data interfaces support 1.544, 2.048 and 4.096 MHz data rates. Each device samples the serial PCM or ADPCM bit stream during a user-programmed input timeslot, processes the data and outputs the result dur- ing a user-programmed output timeslot. Each PCM interface has a control register which speci- fies functional characteristics (compress, expand, by- pass and idle), data format ( µ-law or A-law) and algo- rithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port is used to program control and timeslot registers. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system level interconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps appropriate control register bits to address and port inputs. Under hardware mode, no host controller is required and all PCM I/O defaults to timeslot 0. This stand-alone mode is compatible with popular codecs. DS2168 BLOCK DIAGRAM Figure 1 “X” SIDE PCM/ADPCM DATA INTERFACE SERIAL PORT CONTROL/ HARDWARE MODE LOGIC “Y” SIDE PCM/ADPCM DATA INTERFACE RESET AND TEST LOGIC ADPCM PROCESSING “ENGINE” MCLK VDD VSS FSX CLKX XIN SCLK SPS CS SDI A0 - A5 FSY CLKY YIN YOUT RST TM0 TM1 XOUT |
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