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MC33889 Datasheet(PDF) 48 Page - Freescale Semiconductor, Inc |
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MC33889 Datasheet(HTML) 48 Page - Freescale Semiconductor, Inc |
48 / 60 page Analog Integrated Circuit Device Data 48 Freescale Semiconductor 33889 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 24. Status bits TIM REGISTERS Description: This register is split into 2 sub registers, TIM1 and TIM2. TIM1 controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0. TIM2 is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is 1. No read operation is allowed for registers TIM1 and TIM2 TIM REGISTER Table 25. TIM Register. L0WUb L0WUa FDIS bit in CAN register Description 0 0 0 No wake-up occurred at L0 (sleep or stop mode). Low level state on L0 (standby or normal mode) 1 1 0 Wake-up occurred at L0 (sleep or stop mode). High level state on L0 (standby or normal mode) 0 1 1 Wake-up occurred at L0 (sleep or stop mode with L0 filter disable). WUR must be set to xx00 before sleep or stop mode. L1WUb L1WUa Description 0 0 No wake-up occurred at L1 (sleep or stop mode). Low level state on L1 (standby or normal mode) 1 1 Wake-up occurred at L1 (sleep or stop mode). High level state on L1 (standby or normal mode) TIM1 D3 D2 D1 D0 $101b W 0 WDW WDT1 WDT0 R Reset 0 0 0 Reset condition POR, RESET POR, RESET POR, RESET |
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