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VT82887 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. VT82887
Description  Real Time Clock
Download  17 Pages
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Maker  ETC1 [List of Unclassifed Manufacturers]

VT82887 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

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Real Time Clock
VIA Technologies, Inc.
the VT82887 since the bus change from
address to data occurs during the internal
RAM access time. Addresses must be valid
prior to the falling edge of AS which the
VT82887 uses to latch the address from AD0
to AD6. Valid write data must be present and
held stable during the latter portion of the
RD# or WR# pulses. In a read cycle the
VT82887 outputs 8 bits of data during the
latter portion of the RD# pulse. The read cycle
is terminated and the bus returns to a high
impedance state as RD# transitions high as in
Intel timing.
AS (Address Strobe Input)
− A positive
demultiplex the bus. The falling edge of AS
causes the address to be latched within the
RD# (Read Strobe)
− The low active RD# pin
identifies the time period when the VT82887
drives the bus with read data. The RD# signal
is the same definition as the Output Enable
(OE#) signal on a typical memory.
WR# (Write Strobe)
− The low active WR#
pin is used to indicate a write cycle. The data
on the bus AD0-AD7 at the rising edge of
WR# will be written into VT82887.
CS# (Chip Select Input)
− The Chip Select
signal must be asserted low for a bus cycle in
order that the VT82887 can be accessed.
CS# must be kept in the active state during
RD# and WR#. Bus cycles which take place
without asserting CS# will latch addresses but
no access will occur. When VCC is below 4.25
volts, the VT82887 internally inhibits access
cycles by internally disabling the CS# input.
This action protects both the real time clock
data and RAM data during power outages.
IRQ# (Interrupt Request Output)
− The
IRQ# pin is an active low output of the
VT82887 that can be used as an interrupt
input to a processor. The IRQ# output
remains low as long as the status bit causing
the interrupt is present and the corresponding
interrupt-enable bit is set. To clear the IRQ#
pin the processor program normally reads the
C register. The RESET# pin also clears
pending interrupts.
When no interrupt conditions are present, the
IRQ# level is in the high impedance state.
connected to an IRQ# bus. The IRQ# bus is
an open drain output and requires an external
pull-up resistor.
RESET# (Reset Input)
− The RESET# pin
has no effect on the clock, calendar, or RAM.
On power-up the RESET# pin can be held
low for a time in order to allow the power
supply to stabilize. The amount of time that
RESET# is held low is dependent on the
application. However, if RESET# is used on
power-up, the time RESET# is low should
exceed 200 ms to make sure that the internal
timer that controls the VT82887 on power-up
has timed out. When RESET# is low and VCC
is above 4.25 volts, the following occurs:
A. Periodic Interrupt Enable (PIE) bit is
cleared to zero.
B. Alarm Interrupt Enable (AIE) bit is cleared
to zero.
C. Update Ended Interrupt Flag (UF) bit is
cleared to zero.
D. Interrupt Request Status Flag (IRQF) bit
is cleared to zero.
E. Periodic Interrupt Flag (PF) bit is cleared
to zero.
F. The
RESET# is returned high.
G. Alarm Interrupt Flag (AF) bit is cleared to
H. IRQ# pin is in the high impedance state.
Square Wave Output Enable (SQWE) bit
is cleared to zero.
Update Ended Interrupt Enable (UIE) is
cleared to zero.
In a typical application RESET# can be
connected to VCC. This connection will allow
the VT82887 to go in and out of power fail
without affecting any of the control registers.
The address map of the VT82887 is shown in
Figure 2. The address map consists of 114
bytes of user RAM, 10 bytes of RAM that

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