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VT82887 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part No. VT82887
Description  Real Time Clock
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Maker  ETC1 [List of Unclassifed Manufacturers]
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VT82887 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

 
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VT82887
Real Time Clock
VIA Technologies, Inc.
SIGNAL DESCRIPTIONS
VCC − DC power is provided to the device on
this pin. VCC is the +5 volt input. When 5 volts
are applied within normal limits, the device is
fully accessible and data can be written and
read. When VCC is below 4.25 volts typical,
reads and writes are inhibited. However, the
timekeeping function continues unaffected by
the lower input voltage. As VCC falls below 3
volts typical, the RAM and timekeeper are
switched over to the internal lithium energy
source. The timekeeping function maintains
an accuracy of
± 1 minute per month at 25°C
regardless of the voltage input on the VCC
pin.
SQW (Square Wave Output)
− The SQW
pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of
the Real Time Clock. The frequency of the
SQW pin can be changed by programming
Register A as shown in Table 1. The SQW
signal can be turned on and off using the
SQWE bit in Register B. The SQW signal is
not available when VCC is less than 4.25 volts
typical.
RCLR#
− The RCLR# pin is used to clear (set
to logic 1) all 114 bytes of general purpose
RAM but does not affect the RAM associated
with the real time clock. In order to clear the
RAM, RCLR# must be forced to an input logic
of 0 (-0.3 to +0.8 volts) during battery back-up
mode when VCC is not applied. The RCLR#
function is designed to be used via human
interface (shorting to ground manually or by
switch) and not to be driven with external
buffers. This pin is internally pulled up.
TABLE 1: PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY
SELECT BITS REGISTER A
tPI PERIODIC
SQW OUTPUT
RS3
RS2
RS1
RS0
INTERRUPT RATE
FREQUENCY
0000
None
None
0001
3.90625 ms
256 Hz
0010
7.8125 ms
128 Hz
0011
122.070
µs
8.192 kHz
0100
244.141
µs
4.096 kHz
0101
488.281
µs
2.048 kHz
0110
976.5625
µs
1.024 kHz
0111
1.953125 ms
512 Hz
1000
3.90625 ms
256 Hz
1001
7.8125 ms
128 Hz
1010
15.625 ms
64 Hz
1011
31.25 ms
32 Hz
1100
62.5 ms
16 Hz
1101
125 ms
8 Hz
1110
250 ms
4 Hz
1111
500 ms
2 Hz
AD0-AD7
(Multiplexed
Bidirectional
Address/Data Bus)
− Multiplexed buses
save pins because address information and
data information time share the same signal
paths. The addresses are present during the
first portion of the bus cycle and the same
pins and cycle paths are used for data in the
second portion of the cycle. Address/data
multiplexing does not slow the access time of


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