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SPD6722QCCE Datasheet(PDF) 62 Page - Intel Corporation |
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SPD6722QCCE Datasheet(HTML) 62 Page - Intel Corporation |
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62 / 138 page 
PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers 62 Datasheet 8.6 Card I/O Map 0–1 Offset Address Low There are two separate Card I/O Map Offset Address Low registers, each with identical fields. These registers are located at the following indexes: Index Card I/O Map Offset Address Low 36h Card I/O Map 0 Offset Address Low 38h Card I/O Map 1 Offset Address Low Bits 7:1 — Offset Address 7:1 This register contains the least-significant byte of the quantity that will be added to the host I/O address; this will determine the PC Card I/O map location where the I/O access will occur. The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register (see “Card I/O Map 0–1 Offset Address High” on page 62). 8.7 Card I/O Map 0–1 Offset Address High There are two separate Card I/O Map Offset Address High registers, each with identical fields. These registers are located at the following indexes: Index Card I/O Map Offset Address High 37h Card I/O Map 0 Offset Address High 39h Card I/O Map 1 Offset Address High Register Name: Card I/O Map 0–1 Offset Address Low Index: 36h, 38h Register Per: socket Register Compatibility Type: ext. Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Offset Address 7:1 0 1 RW:0000000 RW:0 1. This bit must be programmed to ‘0’. Register Name: Card I/O Map 0–1 Offset Address High Index: 37h, 39h Register Per: socket Register Compatibility Type: ext. Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Offset Address 15:8 RW:00000000 |
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