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SPD6722QCCE Datasheet(PDF) 58 Page - Intel Corporation

Part No. SPD6722QCCE
Description  ISA-to-PC-Card (PCMCIA) Controllers
Download  138 Pages
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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SPD6722QCCE Datasheet(HTML) 58 Page - Intel Corporation

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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
58
Datasheet
8.0
I/O Window Mapping Registers
The I/O windows must never include 3E0h and 3E1h.
8.1
I/O Window Control
Bit 0 — I/O Window 0 Size
When bit 1 below is ‘0’, this bit determines the size of the data path to I/O Window 0. When bit 1 is
‘1’, this bit is ignored.
Bit 1 — Auto-Size I/O Window 0
This bit determines the data path to I/O Window 0. Note that when this bit is ‘1’, the -IOIS16 signal
(see Table 2 on page 20) determines the width of the data path to the card.
Bit 3 — Timing Register Select 0
This bit determines the access timing specification for I/O Window 0 (see “Setup Timing 0–1” on
page 84).
Register Name: I/O Window Control
Index: 07h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timing
Register
Select 1
Compatibility
Bit
Auto-Size I/O
Window 1
I/O Window 1
Size
Timing
Register
Select 0
Compatibility
Bit
Auto-Size I/O
Window 0
I/O Window 0
Size
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
0
8-bit data path to I/O Window 0.
1
16-bit data path to I/O Window 0.
0
I/O Window 0 Size (see bit 0 above) determines the data path to I/O Window 0.
1
The data path to I/O Window 0 will be determined based on -IOIS16 returned by the card.
0
Accesses made with timing specified in Timing Set 0.
1
Accesses made with timing specified in Timing Set 1.


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