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SPD6722QCCE Datasheet(PDF) 81 Page - Intel Corporation

Part No. SPD6722QCCE
Description  ISA-to-PC-Card (PCMCIA) Controllers
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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SPD6722QCCE Datasheet(HTML) 81 Page - Intel Corporation

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ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Datasheet
81
10.7.4
External Data (PD6722 only, Socket A, Index 2Fh)
Bits 7:0 — External Data
This register is updated and accessed according to the setting of bits 3 and 4 of the Socket A
Extension Control 2 register (Index 2Fh, Extended Index 0Bh).
Note:
For software compatibility of external data access accross the PC Card (PCMCIA) controller
product line, the Socket A External Data register should only be used as a write port and not as a
read port. Also for compatibility, only the lower nibble of External Data should be accessed and
the upper nibble should be ignored.
Refer to “Using GPSTB Pins for External Port Control (PD6722 only)” on page 91 for more
information on the use of the External Data register.
E0h
13 clocks = 520 ns
10h
14 clocks = 560 ns
90h
15 clocks = 600 ns
50h
16 clocks = 640 ns
D0h
17 clocks = 680 ns
30h
18 clocks = 720 ns
B0h
19 clocks = 760 ns
Register Name: External Data
Index: 2Fh only
Extended Index: 0Ah
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
External Data
7
External Data
6
External Data
5
External Data
4
External Data
3
External Data
2
External Data
1
External Data
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Table 14. Maximum DMA Acknowledge Delay Register Values (Sheet 2 of 2)
Register Value
Maximum DMA Acknowledge Delay
(25-MHz internal clock and default Setup timing)
Table 15. Functions of Socket A External Data Register
Socket A Extension Control 2
Function of Socket A External Data Register
Bit 4: GPSTB
on IOW*
Bit 3: GPSTB
on IOR*
0
0
Scratchpad
01
External read port: A_GPSTB is a read buffer enable for external data on
SD[15:8]
10
External write port: A_GPSTB is a write latch enable for SD[15:8] to get
latched to an external register. Reads of Socket A External Data register
produce the value written to the latch.
11
Reserved


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