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SPD6722QCCE Datasheet(PDF) 72 Page - Intel Corporation

Part No. SPD6722QCCE
Description  ISA-to-PC-Card (PCMCIA) Controllers
Download  138 Pages
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Maker  INTEL [Intel Corporation]
Homepage  http://www.intel.com
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SPD6722QCCE Datasheet(HTML) 72 Page - Intel Corporation

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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
72
Datasheet
10.2
FIFO Control
Bit 7 — Empty Write FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is written to ‘1’, all data in
the FIFO is lost. During read operations when this bit is ‘1’, the FIFO is empty. During read
operations when this bit is ‘0’, data is still in the FIFO. This bit is used to ensure the FIFO is empty
before changing timing registers.
FIFO contents will be lost whenever any of the following occur:
PWRGOOD pin ( Table 1) is ‘0’.
The card is removed.
VCC Power bit (see “Bit 4 — VCC Power” on page 50) is programmed to ‘0’.
10.3
Misc Control 2
Register Name: FIFO Control
Index: 17h
Register Per: socket
Register Compatibility Type: ext.
Bit 7Bit 6Bit 5
Bit 4Bit 3Bit 2
Bit 1Bit 0
Empty Write
FIFO
Scratchpad Bitsa
a.
RW
RW:0000000
1. Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
Value
I/O Read
I/O Write
0
FIFO not empty
No operation occurs; default on reset
1
FIFO empty
Flush the FIFO
Register Name: Misc Control 2
Index: 1Eh
Register Per: chip
Register Compatibility Type: ext.
Bit 7Bit 6Bit 5Bit 4Bit 3
Bit 2Bit 1
Bit 0
IRQ15 Is RI
Out
DMA System
(PD6722)
Three-State
Bit 7
Drive LED
Enable
5V Core
Suspend
Low-Power
Dynamic
Mode
Bypass
Frequency
Synthesizer
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:1
RW:0


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